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HEF4081BT,118 PDF预览

HEF4081BT,118

更新时间: 2024-11-04 20:04:35
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
11页 120K
描述
AND Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, PDSO14

HEF4081BT,118 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.68
系列:4000/14000/40000JESD-30 代码:R-PDSO-G14
长度:8.65 mm逻辑集成电路类型:AND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):110 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

HEF4081BT,118 数据手册

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HEF4081B  
Quad 2-input AND gate  
Rev. 8 — 15 December 2015  
Product data sheet  
1. General description  
The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest  
noise immunity and pattern insensitivity to output impedance variations.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Inputs and outputs are protected against electrostatic effects  
Specified from40 C to +85 C and 40 C to +125 C  
Complies with JEDEC standard JESD 13-B  
3. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +125 C.  
Type number  
Package  
Name  
Description  
Version  
HEF4081BT  
SO14  
plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
4. Functional diagram  
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Fig 1. Functional diagram  
Fig 2. Logic diagram (one gate)  

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