HDMP-1546

更新时间： 2024-09-15 22:33:19

品牌	Logo	应用领域
安捷伦 - AGILENT		光纤电信集成电路电信电路
页数	文件大小	规格书
15页	259K
描述
Fibre Channel Transceiver Chip

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中文翻译

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技术参数
数据手册

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HDMP-1546 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP64,.66SQ,32	Reach Compliance Code：	unknown
风险等级：	5.78	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
端子数量：	64	最高工作温度：	60 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP64,.66SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

HDMP-1546 数据手册

Fibre Channel Transceiver Chip

Technical Data

HDMP-1536 Transceiver

HDMP-1546 Transceiver

Features

• ANSI X3.230-1994 Fibre

Channel Compatible (FC-0)

Description

The HDMP-1536/46 transceiver

is a single silicon bipolar

• Supports Full Speed

(1062.5 MBd) Fibre Channel

integrated circuit packaged in a

plastic QFP package. It provides

a low-cost, low-power physical

layer solution for 1062.5 MBd

Fibre Channel or proprietary link

interfaces. It provides complete

FC-0 functionality for copper

transmission, incorporating both

the Fibre Channel FC-0 transmit

and receive functions into a

single device.

• Compatible with “Fibre

Channel 10-Bit Interface”

Specification

• Low Power Consumption,

630 mW

• Transmitter and Receiver

Functions Incorporated onto

a Single IC

• Auto Frequency Lock

• Small Package Profile

The transmitter section’s PLL

locks to this user supplied 106.25

MHz byte clock. This clock is

then multiplied by 10, to generate

the 1062.5 MHz serial signal

clock used to generate the high-

speed output. The high-speed

outputs are capable of interfacing

directly to copper cables for

electrical transmission or to a

separate fiber-optic module for

optical transmission.

This chip is used to build a high-

speed interface (as shown in

Figure 1) while minimizing board

space, power, and cost. It is

compatible with both the ANSI

X3.230-1994/AM 1 - 1996

HDMP-1536, 10x10 mm QFP

HDMP-1546, 14x14 mm QFP

• 10-Bit Wide Parallel TTL

Compatible I/Os

• Single +3.3 V Power Supply

document and the “Fibre Channel

10-bit Interface” specification.

Applications

• 1062.5 MBd Fibre Channel

Interface

• FC Interface for Disk Drives

and Arrays

• Mass Storage System I/O

Channel

• Work Station/Server I/O

Channel

• High Speed Proprietary

Interface

• High Speed Backplane

Interface

The transmitter section accepts

10-bit wide parallel TTL data and

multiplexes this data into a high-

speed serial data stream. The

parallel data is expected to be

8B/10B encoded data, or

equivalent. This parallel data is

latched into the input register of

the transmitter section on the

rising edge of the 106.25 MHz

reference clock (used as the

transmit byte clock).

The receiver section accepts a

serial electrical data stream at

1062.5 MBd and recovers the

original 10-bit wide parallel data.

The receiver PLL locks onto the

incoming serial signal and

recovers the high-speed serial

clock and data. The serial data is

696

5965-8113E (4/97)

12 3 4 5 6 7...15

中文翻译

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与HDMP-1546相关器件

型号	品牌	获取价格	描述	数据表
HDMP-1546A	ETC	获取价格	IC-TRANSCEIVER
HDMP-1546AG	PMC	获取价格	Telecom IC, Bipolar, PQFP64,
HDMP-1636	AGILENT	获取价格	Gigabit Ethernet Transceiver Chip
HDMP-1636A	AGILENT	获取价格	Gigabit Ethernet and Fibre Channel SerDes ICs
HDMP-1636AG	PMC	获取价格	Ethernet Transceiver, 1-Trnsvr, PQFP64, 10 MM, LEAD FREE, PLASTIC, QFP-64
HDMP-1637A	AGILENT	获取价格	Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs
HDMP-1638	AGILENT	获取价格	Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs
HDMP-1638G	PMC	获取价格	Ethernet Transceiver, 1-Trnsvr, Bipolar, PQFP64,
HDMP-1646	AGILENT	获取价格	Gigabit Ethernet Transceiver Chip
HDMP-1646A	AGILENT	获取价格	Gigabit Ethernet and Fibre Channel SerDes ICs

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