Datasheet > HDMP-1685AG

HDMP-1685AG

更新时间： 2024-01-28 12:39:18

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
20页	254K
描述
Telecom IC, Bipolar, PBGA208,

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技术参数
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HDMP-1685AG 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.7
JESD-30 代码：	S-PBGA-B208	端子数量：	208
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA208,17X17,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	Base Number Matches：	1

HDMP-1685AG 数据手册

Agilent HDMP-1685A

1.25 Gbps Four Channel SerDes

with 5-pin DDR SSTL_2

Parallel Interface

Data Sheet

Features

• 5-bit wide Tx, Rx bus pairs

• 208-ball, 23 mm TBGA package

• Parallel data I/O and clocks

compatible with SSTL_2

(EIA/JESD8-9)

• 125 MHz TC, RC clocks

• One TC clock for 4 channels

• Single or paired RC clocks

• LVTTL RefClk input

• Source synchronous clocking of

transmit data

• Source centered clocking of

receive data

• Double data rate (DDR) parallel

transfers

• Parallel loopback

• Differential BLL serial I/O

• Single +3.3 V power supply

• Copper drive capability

Functional Description

The transmitter section accepts

four, 5-bit-wide parallel SSTL_2

data (TX [0:3] [0:4]), a 125 MHz

SSTL_2 byte clock (TC) and seri-

alizes them into four high-speed

serial streams. The parallel data

is expected to be “8B/10B” en-

coded data, or equivalent. TX and

TC are source synchronous. New

data are accepted on both edges

of TC; this is called Double Data

Rate (DDR). HDMP-1685A finds

a sampling window in between

the two edges of TC to latch

This data sheet describes HDMP-

1685A, a 1.25 Gbps, four-channel,

5-pin per channel parallel interface

SERDES device. The HDMP-1685A

5-pin parallel interface device en-

ables a single ASIC to drive twice as

many channels using half as many

parallel lines. This is accomplished

without increasing the clock

frequency by utilizing the bandwidth

on the parallel interface more

efficiently.

Applications

• High density fast ports

• Fast serial backplanes

• Clusters of computers

• Clusters of network units

• Link aggregation, trunks

TX [0:3] [0:4] data into the input

The HDMP-1685A SERDES is a

single silicon bipolar integrated

circuit packaged in a 208-pin BGA.

This integrated circuit provides a

low-cost, small-form-factor physical-

layer solution for multi-link

1.25 Gbps cables or optical trans-

ceivers. Each IC contains transmit

and receive channel circuitry for all

four channels.

This timing scheme assumes that

the driving ASIC and HDMP-1685A

operate in the same clock domain. The transmitter section’s PLL

8B/10B encoded data comes in

10-bit characters. This data is

locks to the 125 MHz TC. This

clock is then multiplied by 10 to

latched onto the 5 TX pins of each generate the 1250 MHz serial

channel in 5-bit groups. It is ex-

pected that the beginning half of

clock for the high-speed serial

outputs. The high-speed outputs

each 10-bit character is latched on are capable of interfacing directly

A 125 MHz LVTTL reference clock

must be supplied to the reference

clock input pin, RFCT.

the rising edge of TC.

to copper cables for electrical

transmission or to a separate fiber

optic module for optical

transmission.

12 3 4 5 6 7...20

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