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HD74LS160AFP-EL PDF预览

HD74LS160AFP-EL

更新时间: 2024-11-10 13:08:19
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
11页 204K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, FP-16DA

HD74LS160AFP-EL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.68
计数方向:UP系列:LS
JESD-30 代码:R-PDSO-G16长度:10.06 mm
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
工作模式:SYNCHRONOUS湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):27 ns认证状态:Not Qualified
座面最大高度:2.2 mm标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL EXTENDED端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.5 mm最小 fmax:25 MHz
Base Number Matches:1

HD74LS160AFP-EL 数据手册

 浏览型号HD74LS160AFP-EL的Datasheet PDF文件第2页浏览型号HD74LS160AFP-EL的Datasheet PDF文件第3页浏览型号HD74LS160AFP-EL的Datasheet PDF文件第4页浏览型号HD74LS160AFP-EL的Datasheet PDF文件第5页浏览型号HD74LS160AFP-EL的Datasheet PDF文件第6页浏览型号HD74LS160AFP-EL的Datasheet PDF文件第7页 
HD74LS160A  
Synchronous Decade Counter (direct clear)  
REJ03D0444–0300  
Rev.3.00  
Jul.15.2005  
This synchronous decade counter features an internal carry look ahead for application in high-speed counting designs.  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes  
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation  
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A  
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This  
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up  
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock  
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of this device should be  
avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is  
asynchronous and a low level at the clear input sets all four of the flip-flop outputThe carry look-ahead circuitry  
provides for cascading counters for n-bit synchronous applications without addgetting. Instrumental in  
accomplishing this function is two count-enable inputs and a ripple carry ouunt-enable inputs (P and T)  
must be high to count, and input T is fed forward to enable the ripple care carry output thus enabled  
will produced a high-level output pulse with a duration approximately ortion of the QA output.  
This high-level overflow ripple carry pulse can be used to enable sHigh-to-low-level  
transitions at the enable P or T inputs should occur only when t
Features  
Ordering Information  
kage  
bbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
HD74LS160AP  
HD74LS160AFPEL  
P
-B  
)  
SOP-16 p
FP  
EL (2,000 pcs/reel)  
Note: Please consult the saage availability.  
Pin Arrangement  
Clea
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
CLR  
Ripple  
Carry  
Ripple  
Carry Output  
CK  
Clock  
A
Q
A
B
QA  
QB  
QC  
QD  
A
B
B
C
Q
Data  
Inputs  
Outputs  
Q
C
D
C
D
D
P
Q
T
Enable P  
GND  
Enable T  
Load  
Load  
(Top view)  
Rev.3.00, Jul.15.2005, page 1 of 10  

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