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HD74LS162A PDF预览

HD74LS162A

更新时间: 2024-09-21 05:35:15
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瑞萨 - RENESAS 计数器
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11页 201K
描述
Synchronous Decade Counter (synchronous clear)

HD74LS162A 数据手册

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HD74LS162A  
Synchronous Decade Counter (synchronous clear)  
REJ03D0446–0300  
Rev.3.00  
Jul.15.2005  
This synchronous decade counter features an internal carry look-ahead for application in high-speed counting designs.  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes  
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation  
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A  
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This  
counter is fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting  
up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next  
clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided  
when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a  
low level at the clear input sets all four of the flip-flop outputs low after the next cck pulse, regardless of the levels of  
the enable inputs. This synchronous clear allows the count length to be modifiy as decoding the maximum  
count desired can be accomplished with one external NAND gate. The gate nected to the clear input to  
synchronously clear the counter to LLLL. Low-to-high transitions at the be avoided when the clock  
is low if the enable and load inputs are high at or before the transitionrcuitry provides for  
cascading counters for n-bit synchronous applications without addin accomplishing this  
function are two count-enable inputs and a ripple carry output. and T) must be high to  
count, and input T is fed forward to enable the ripple carry out thus enabled will produce a  
high-level output pulse with a duration approximately equof the QA output. This high-level  
overflow ripple carry pulse can be used to enable succ-to-low-level transitions at the  
enable P or T inputs should occur only when the clo
Features  
Ordering Information  
e  
Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package T
16DH-B  
6DAV)  
HD74LS162AFPEL  
SOP
FP  
EL (2,000 pcs/reel)  
Rev.3.00, Jul.15.2005, page 1 of 10  

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