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HD74LS161AP PDF预览

HD74LS161AP

更新时间： 2024-09-21 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 106K
描述
Synchronous 4-bit Binary Counter (direct clear)

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中文翻译

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HD74LS161AP 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.17
计数方向：UP系列：LS
JESD-30 代码：R-PDIP-T16长度：19.2 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：25000000 Hz最大I（ol）：0.008 A
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：75 °C
最低工作温度：-20 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：32 mA传播延迟（tpd）：27 ns
认证状态：Not Qualified座面最大高度：5.06 mm
子类别：Counters最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL EXTENDED端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：25 MHz
Base Number Matches：1

HD74LS161AP 数据手册

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HD74LS161A  
Synchronous 4-bit Binary Counter (direct clear)  
REJ03D0445–0200  
Rev.2.00  
Feb.18.2005  
This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting  
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes  
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation  
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A  
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This  
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up  
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock  
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided when the  
clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level  
at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The  
carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting.  
Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable  
inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry  
output thus enabled will produced a high-level output pulse with a duration approximately equal to the high-level  
portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages.  
High-to-low-level transitions at the enable P or T inputs should occur only when the clock input is high.  
Features  
•
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS161AP  
HD74LS161AFPEL  
HD74LS161ARPEL  
DILP-16 pin  
P
—
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 10  
1234567...11

中文翻译

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HD74LS161AP 替代型号

型号 品牌 替代类型 描述 数据表
HD74LS161AFP RENESAS

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