Datasheet > 逻辑 > 计数器> HD74LS162AFP-EL

HD74LS162AFP-EL

更新时间： 2024-09-21 13:08:19

品牌	Logo	应用领域
瑞萨 - RENESAS		计数器
页数	文件大小	规格书
11页	201K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, FP-16DA

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HD74LS162AFP-EL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.7
计数方向：	UP	系列：	LS
JESD-30 代码：	R-PDSO-G16	长度：	10.06 mm
负载/预设输入：	YES	逻辑集成电路类型：	DECADE COUNTER
工作模式：	SYNCHRONOUS	湿度敏感等级：	1
位数：	4	功能数量：	1
端子数量：	16	最高工作温度：	75 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	27 ns	认证状态：	Not Qualified
座面最大高度：	2.2 mm	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL EXTENDED	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	触发器类型：	POSITIVE EDGE
宽度：	5.5 mm	最小 fmax：	25 MHz
Base Number Matches：	1

HD74LS162AFP-EL 数据手册

HD74LS162A

Synchronous Decade Counter (synchronous clear)

REJ03D0446–0300

Rev.3.00

Jul.15.2005

This synchronous decade counter features an internal carry look-ahead for application in high-speed counting designs.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes

coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation

eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This

counter is fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting

up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next

clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided

when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a

low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of

the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum

count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to

synchronously clear the counter to LLLL. Low-to-high transitions at the clear input should be avoided when the clock

is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for

cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this

function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to

count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a

high-level output pulse with a duration approximately equal to the high-level portion of the Q_Aoutput. This high-level

overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the

enable P or T inputs should occur only when the clock input is high.

Features

•

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

PRSP0016DH-B

(FP-16DAV)

HD74LS162AFPEL

SOP-16 pin (JEITA)

EL (2,000 pcs/reel)

Rev.3.00, Jul.15.2005, page 1 of 10

12 3 4 5 6 7...11

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与HD74LS162AFP-EL相关器件

型号	品牌	获取价格	描述	数据表
HD74LS162AP	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, DP-16
HD74LS162ARP	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, FP-16DN
HD74LS162P	ETC	获取价格	Synchronous Up Counter
HD74LS163	ETC	获取价格	Synchronous Up Counter
HD74LS163A	RENESAS	获取价格	Synchronous 4-bit Binary Counter (direct clear)
HD74LS163A	HITACHI	获取价格	Synchronous 4-bit Binary Counters(synchronous clear)
HD74LS163AFP	ETC	获取价格	COUNTER\|UP\|4-BIT BINARY\|LS-TTL\|SOP\|16PIN\|PLASTIC
HD74LS163AFPEL	RENESAS	获取价格	Synchronous 4-bit Binary Counter (direct clear)
HD74LS163AFP-EL	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, FP-16DA
HD74LS163AFP-EL	HITACHI	获取价格	暂无描述

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