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HD74LS163ARPEL PDF预览

HD74LS163ARPEL

更新时间: 2024-11-08 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
12页 199K
描述
Synchronous 4-bit Binary Counter (direct clear)

HD74LS163ARPEL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.54
计数方向:UP系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.008 A工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:5 V
最大电源电流(ICC):32 mA传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL EXTENDED端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.95 mm最小 fmax:25 MHz

HD74LS163ARPEL 数据手册

 浏览型号HD74LS163ARPEL的Datasheet PDF文件第2页浏览型号HD74LS163ARPEL的Datasheet PDF文件第3页浏览型号HD74LS163ARPEL的Datasheet PDF文件第4页浏览型号HD74LS163ARPEL的Datasheet PDF文件第5页浏览型号HD74LS163ARPEL的Datasheet PDF文件第6页浏览型号HD74LS163ARPEL的Datasheet PDF文件第7页 
HD74LS163A  
Synchronous 4-bit Binary Counter (direct clear)  
REJ03D0447–0200  
Rev.2.00  
Feb.18.2005  
This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting  
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes  
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation  
eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A  
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This  
counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up  
a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock  
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input would be avoided when the  
clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level  
at the clear input sets all four of the flip-flop outputs low after the next clock pulsregardless of the levels of the enable  
inputs. This synchronous clear allows the count length to be modified easily ang the maximum count desired  
can be accomplished with one external NAND gate. The gate output is conlear input to synchronously  
clear the counter to LLLL. Low-to-high transitions at the clear input shon the clock is low if the  
enable and load inputs are high at or before the transition. The carry des for cascading  
counters for n-bit synchronous applications without additional gettlishing this function are  
two count-enable inputs and a ripple carry output. Both count-ebe high to count, and input  
T is fed forward to enable the ripple carry output. The ripple ill produce a high-level output  
pulse with a duration approximately equal to the high-levThis high-level overflow ripple  
carry pulse can be used to enable successive cascaded ansitions at the enable P or T inputs  
should occur only when the clock input is high.  
Features  
Ordering Information  
e  
Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package T
16AE-B  
16FV)  
HD74LS163AP  
HD74LS163AFPEL  
HD74LS163ARPEL  
DIL
P
RSP0016DH-B  
(FP-16DAV)  
SO
SOP-16 )  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Rev.2.00, Feb.18.2005, page 1 of 11  

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