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HD74LS164P PDF预览

HD74LS164P

更新时间: 2024-09-22 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 移位寄存器
页数 文件大小 规格书
9页 91K
描述
8-Bit Parallel-Out Serial-in Shift Register

HD74LS164P 数据手册

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HD74LS164  
8-Bit Parallel-Out Serial-in Shift Register  
REJ03D0448–0200  
Rev.2.00  
Feb.18.2005  
This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit  
complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the  
first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them  
determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but  
only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of  
the clock input.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0014AB-B  
(DP-14AV)  
HD74LS164P  
DILP-14 pin  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74LS164FPEL  
HD74LS164RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
A
B
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
Serial  
Inputs  
A
B
QH  
Q
Q
Q
Q
H
G
F
QA  
Q
Q
Q
Q
A
B
C
D
QG  
Outputs  
QB  
Q
F
Outputs  
QE  
Q
Q
C
D
E
CLR  
Clear  
Clock  
CK  
8
GND  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 8  

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