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HD74LS166AP PDF预览

HD74LS166AP

更新时间: 2024-09-22 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 101K
描述
8-bit Shift Register

HD74LS166AP 数据手册

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HD74LS166A  
8-bit Shift Register  
REJ03D0450-0400  
Rev.4.00  
May 10, 2006  
The inputs are buffered to lower the drive requirements to one series 74 or 74LS standard load, respectively. Input  
clamping diodes minimize switching transients and simplify system design. This parallel in or serial-in, serial-out shift  
register has a complexity of 77 equivalent gates on a monolithic chip. This device features gated clock inputs and an  
overriding clear input.  
The parallel-in or serial-in modes are established by the shift / load input.  
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock  
pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock  
pulse, during parallel loading, serial data flow is inhibited.  
This, of course, allows the system clock to be free running and the register can be stopped on command with the other  
clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered,  
direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS166AP  
DILP-16 pin  
P
Pin Arrangement  
Serial  
Input  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
Shift/  
Load  
A
B
Parallel  
Input H  
Parallel  
Inputs  
C
D
Output Q  
H
G
Clock  
Inhibit  
Parallel  
Inputs  
F
E
Clock  
GND  
Clear  
(Top view)  
Rev.4.00, May 10, 2006, page 1 of 7  

HD74LS166AP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS166ANE4 TI

功能相似

LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, ROHS CO

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