HCTS32MS
Radiation Hardened
Quad 2-Input OR Gate
September 1995
Features
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
A1
B1
1
2
3
4
5
6
7
14 VCC
13 B4
12 A4
11 Y4
10 B3
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
Y1
A2
B2
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
Y2
9
8
A3
Y3
GND
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA @ VOL, VOH
A1
B1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
B4
A4
Y4
Y1
Description
A2
The Intersil HCTS32MS is a Radiation Hardened Quad 2-Input OR
Gate. A Low on all inputs forces the output to a Low state.
B2
B3
A3
Y3
Y2
The HCTS32MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
8
The HCTS32MS is supplied in a 14 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
Functional Diagram
An
(1, 4, 9, 12)
Ordering Information
Yn
(3, 6, 8, 11)
PART
NUMBER
TEMPERATURE SCREENING
RANGE LEVEL
PACKAGE
Bn
o
o
HCTS32DMSR
-55 C to +125 C Intersil Class
S Equivalent
14 Lead SBDIP
(2, 5, 10, 13)
o
o
HCTS32KMSR
-55 C to +125 C Intersil Class
S Equivalent
14 Lead
Ceramic
Flatpack
TRUTH TABLE
INPUTS
OUTPUTS
o
HCTS32D/
Sample
+25 C
Sample
Sample
14 Lead SBDIP
An
L
Bn
L
Yn
L
o
HCTS32K/
Sample
+25 C
14 Lead
Ceramic
Flatpack
L
H
L
H
H
H
H
o
HCTS32HMSR
+25 C
Die
Die
H
H
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518638
File Number 2248.2
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