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HCTS373D

更新时间： 2024-11-01 22:55:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 锁存器
页数 文件大小 规格书
11页 280K
描述
Radiation Hardened Octal Transparent Latch, Three-State

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HCTS373D 数据手册

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HCTS373MS  
Radiation Hardened  
Octal Transparent Latch, Three-State  
August 1995  
Features  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T20  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-  
Day (Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
1
2
3
4
5
6
7
8
9
VCC  
Q7  
OE  
Q0  
D0  
D1  
Q1  
Q2  
D2  
D3  
Q3  
20  
19  
18 D7  
17 D6  
16 Q6  
15  
Q5  
• Fanout (Over Temperature Range)  
- Bus Driver Outputs - 15 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
14 D5  
13 D4  
12  
Q4  
GND 10  
11 LE  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
20 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F20  
TOP VIEW  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
Description  
The Intersil HCTS373MS is a Radiation Hardened octal transpar-  
ent three-state latch with an active-low output enable. The out-  
puts are transparent to the inputs when the Latch Enable (LE) is  
HIGH. When the Latch Enable (LE) goes LOW, the data is  
latched. The Output Enable (OE) controls the three-state outputs.  
When the Output Enable (OE) is HIGH, the outputs are in the  
high impedance state. The latch operation is independent of the  
state of the Output Enable.  
OE  
Q0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
Q7  
D7  
D6  
Q6  
Q5  
D5  
D4  
Q4  
LE  
D0  
D1  
Q1  
Q2  
D2  
D3  
The HCTS373MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Q3  
GND  
The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K  
suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART NUMBER  
HCTS373DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
20 Lead SBDIP  
o
o
HCTS373KMSR  
-55 C to +125 C  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
HCTS373D/Sample  
HCTS373K/Sample  
HCTS373HMSR  
+25 C  
o
+25 C  
Sample  
20 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518636  
File Number 2131.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999638  
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与HCTS373D相关器件

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HCTS373DMSH RENESAS

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 		IC,LATCH,SINGLE,8-BIT,CMOS, RAD HARD,DIP,20PIN,CERAMIC
HCTS373DMSR INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373DTR INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373HMSR INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373K INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373KMSR INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373KTR INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373MS INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS373T INTERSIL

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 		Radiation Hardened Octal Transparent Latch, Three-State
HCTS374D INTERSIL

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 		Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered

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