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HCTS245K/SAMPLE

更新时间： 2024-11-02 14:50:47
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路
页数 文件大小 规格书
9页 169K
描述
HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20

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HCTS245K/SAMPLE 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknown风险等级：5.59
Is Samacsys：N系列：HCT
JESD-30 代码：R-CDFP-F20逻辑集成电路类型：BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：20
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：21 ns认证状态：Not Qualified
座面最大高度：2.92 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.92 mm
Base Number Matches：1

HCTS245K/SAMPLE 数据手册

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TM  
HCTS245MS  
Radiation Hardened  
Octal Bus Transceiver, Three-State, Non-Inverting  
September 1995  
Features  
Pinouts  
• 3 Micron Radiation Hardened CMOS SOS  
20 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T20  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
TOP VIEW  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/  
Bit-Day (Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
OE  
B0  
B1  
B2  
B3  
B4  
B5  
DIR  
A0  
3
A1  
4
A2  
5
A3  
6
A4  
• Fanout (Over Temperature Range)  
- Bus Driver Outputs - 15 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
7
A5  
8
A6  
9
A7  
B6  
B7  
10  
GND  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
20 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F20  
TOP VIEW  
- VIH = VCC/2 Min  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
Description  
VCC  
OE  
B0  
B1  
B2  
B3  
B4  
B5  
DIR  
A0  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
The Intersil HCTS245MS is a Radiation Hardened Non-  
Inverting Octal Bidirectional Bus Transceiver, Three-State,  
intended for two-way asynchronous communication between  
data busses. The HCTS245MS allows data transmission  
from the A bus to the B bus or from the B bus to the A bus.  
The logic level at the direction input (DIR) determines the  
data direction. The output enable input (OE) puts the I/O port  
in the high-impedance state when high.  
2
A1  
3
A2  
4
A3  
5
A4  
6
A5  
7
A6  
8
9
A7  
B6  
B7  
The HCTS245MS utilizes advanced CMOS/SOS technology  
to achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
10  
GND  
The HCTS245MS is supplied in a 20 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART NUMBER  
HCTS245DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
PACKAGE  
20 Lead SBDIP  
o
o
-55 C to +125 C  
Intersil Class S Equivalent  
o
o
HCTS245KMSR  
-55 C to +125 C  
Intersil Class S Equivalent  
20 Lead Ceramic Flatpack  
20 Lead SBDIP  
o
HCTS245D/Sample  
HCTS245K/Sample  
HCTS245HMSR  
+25 C  
Sample  
Sample  
Die  
o
+25 C  
20 Lead Ceramic Flatpack  
Die  
o
+25 C  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518615  
File Number 2360.2  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
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HCTS273K/SAMPLE RENESAS

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