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HCTS27MS

更新时间： 2024-11-01 22:55:03
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英特矽尔 - INTERSIL 栅
页数 文件大小 规格书
9页 58K
描述
Radiation Hardened Triple 3-Input NOR Gate

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HCTS27MS 数据手册

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HCTS27MS  
Radiation Hardened  
Triple 3-Input NOR Gate  
September 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL  
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 C1  
12 Y1  
11 C3  
10 B3  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
A2  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
B2  
C2  
Y2  
9
8
A3  
Y3  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
GND  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP3-F14  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
C1  
Y1  
- VIH = VCC/2 Min  
A2  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
B2  
C3  
B3  
A3  
Y3  
C2  
Description  
Y2  
The Intersil HCTS27MS is a Radiation Hardened Triple 3-Input  
NOR Gate. A Low on all inputs forces the output to a High state.  
GND  
8
The HCTS27MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
Functional Diagram  
An  
The HCTS27MS is supplied in a 14 lead Ceramic flatpack (K  
suffix) or a SBDIP Package (D suffix).  
Bn  
Cn  
Yn  
Ordering Information  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
TRUTH TABLE  
INPUTS  
o
o
HCTS27DMSR  
HCTS27KMSR  
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead SBDIP  
OUTPUTS  
An  
L
Bn  
L
Cn  
L
Yn  
H
L
o
o
-55 C to +125 C Intersil Class  
S Equivalent  
14 Lead  
Ceramic  
Flatpack  
L
L
H
L
L
H
H
L
L
o
HCTS27D/  
Sample  
+25 C  
Sample  
Sample  
14 Lead SBDIP  
L
H
L
L
H
H
H
H
L
o
HCTS27K/  
Sample  
+25 C  
14 Lead  
Ceramic  
Flatpack  
L
H
L
L
H
H
L
H
L
o
HCTS27HMSR  
+25 C  
Die  
Die  
NOTE: L = Logic Level Low, H = Logic level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518643  
File Number 3055.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999430  
1234567...9

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