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HCTS193DMSR

更新时间： 2024-11-01 22:55:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 计数器
页数 文件大小 规格书
9页 161K
描述
Radiation Hardened Synchronous 4-Bit Up/Down Counter

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HCTS193DMSR 数据手册

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HCTS193MS  
Radiation Hardened  
Synchronous 4-Bit Up/Down Counter  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-  
Day (Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse  
VCC  
P0  
P1  
Q1  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
Q0  
MR  
• Latch-Up Free Under Any Conditions  
CPD  
CPU  
Q2  
TCD  
• Fanout (Over Temperature Range)  
- Standard Outputs - 10 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
12 TCU  
PL  
11  
10 P2  
P3  
Q3  
GND  
9
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
16 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F16  
TOP VIEW  
Description  
The Intersil HCTS193MS is a Radiation Hardened 4-bit binary  
UP/DOWN synchronous counter.  
VCC  
P0  
P1  
Q1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Presetting the counter to the number on the preset data inputs  
(P0 - P3) is accomplished by a low on the asynchronous parallel  
load input (PL). The counter is incremented on the low to high  
transition of the clock-up input (high on the clock-down),  
decremented on the low to high transition of the clock-down input  
(high on the clock-up). A high level on the MR input overrides any  
other input to clear the counter to zero. The Terminal Count Up  
goes low half a clock period before the zero count is reached and  
returns high at the maximum count. The Terminal Count Down  
mode goes low half a clock period before the maximum count  
and returns high at the maximum count.  
Q0  
MR  
TCD  
TCU  
PL  
CPD  
CPU  
Q2  
P2  
Q3  
P3  
GND  
The HCTS193MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
The HCTS193MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART NUMBER  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
HCTS193DMSR  
-55 C to +125 C  
16 Lead SBDIP  
o
o
HCTS193KMSR  
-55 C to +125 C  
16 Lead Ceramic Flatpack  
16 Lead SBDIP  
o
HCTS193D/Sample  
HCTS193K/Sample  
HCTS193HMSR  
+25 C  
o
+25 C  
Sample  
16 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518620  
File Number 3066.1  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
592  
1234567...9

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