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HCTS20MS PDF预览

HCTS20MS

更新时间: 2024-11-01 22:55:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL
页数 文件大小 规格书
8页 218K
描述
Radiation Hardened Dual 4-Input NAND Gate

HCTS20MS 数据手册

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TM  
HCTS20MS  
Radiation Hardened  
Dual 4-Input NAND Gate  
September 1995  
Features  
Pinouts  
• 3 Micron Radiation Hardened SOS CMOS  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL  
PACKAGE (SBDIP) MIL-STD-183S CDIP2-T14  
TOP VIEW  
• Total Dose 200K RAD (Si)  
2
• SEP Effective LET No Upsets: >100 MEV-cm /mg  
-9  
• Single Event Upset (SEU) Immunity < 2 x 10 Errors/Bit-Day  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 D2  
12 C2  
11 NC  
10 B2  
(Typ)  
12  
• Dose Rate Survivability: >1 x 10 RAD (Si)/s  
10  
NC  
C1  
• Dose Rate Upset >10 RAD (Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
o
o
• Military Temperature Range: -55 C to +125 C  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• LSTTL Input Compatibility  
D1  
Y1  
9
8
A2  
Y2  
GND  
- VIL = 0.8V Max  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-183S CDFP3-F14  
TOP VIEW  
- VIH = VCC/2 Min  
• Input Current Levels Ii 5µA at VOL, VOH  
Description  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
D2  
The Intersil HCTS20MS is a Radiation Hardened Dual 4-Input  
NAND Gate. A low on any input forces the output to a High state.  
The HCTS20MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family.  
NC  
C1  
C2  
NC  
B2  
D1  
Y1  
A2  
The HCTS20MS is supplied in a 14 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
GND  
8
Y2  
Functional Diagram  
Ordering Information  
An  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
HCTS20DMSR -55oC to +125oC Intersil Class  
S Equivalent  
14 Lead SBDIP  
Bn  
Cn  
Dn  
Yn  
HCTS20KMSR -55oC to +125oC Intersil Class  
S Equivalent  
14 Lead Ceramic  
Flatpack  
HCTS20D/  
Sample  
+25oC  
+25oC  
+25oC  
Sample  
Sample  
Die  
14 Lead SBDIP  
HCTS20K/  
Sample  
14 Lead Ceramic  
Flatpack  
TRUTH TABLE  
INPUTS  
OUTPUTS  
HCTS20HMSR  
Die  
An  
L
Bn  
Cn  
X
Dn  
X
Yn  
H
H
H
H
L
X
L
X
X
X
X
X
X
H
L
X
X
X
L
H
H
H
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518619  
FN3051.1  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
420  

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