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HCTS21MS

更新时间： 2024-11-01 22:55:03
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英特矽尔 - INTERSIL 栅
页数 文件大小 规格书
9页 151K
描述
Radiation Hardened Dual 4-Input AND Gate

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HCTS21MS 数据手册

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HCTS21MS  
Radiation Hardened  
Dual 4-Input AND Gate  
October 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-183S CDIP2-T14, LEAD FINISH C  
TOP VIEW  
• 3 Micron Radiation Hardened SOS CMOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day  
(Typ)  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 D2  
12 C2  
11 NC  
10 B2  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse  
• Latch-Up Free Under Any Conditions  
NC  
C1  
D1  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
Y1  
9
8
A2  
Y2  
GND  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
A1  
B1  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
D2  
- VIH = VCC/2 Min  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
NC  
C1  
C2  
NC  
B2  
D1  
Description  
Y1  
A2  
The Intersil HCTS21MS is a Radiation Hardened Dual Input AND  
Gate. A high on all inputs forces the output to a High state.  
GND  
8
Y2  
The HCTS21MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of radia-  
tion hardened, high-speed, CMOS/SOS Logic Family.  
Functional Diagram  
An  
The HCTS21MS is supplied in a 14 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Bn  
Cn  
Dn  
Yn  
Ordering Information  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
o
o
HCTS21DMSR -55 C to +125 C Intersil Class  
S Equivalent  
14 Lead SBDIP  
TRUTH TABLE  
INPUTS  
OUTPUTS  
o
o
HCTS21KMSR -55 C to +125 C Intersil Class  
S Equivalent  
14 Lead Ceramic  
Flatpack  
An  
L
Bn  
Cn  
X
Dn  
X
Yn  
L
X
L
o
HCTS21D/  
Sample  
+25 C  
Sample  
Sample  
Die  
14 Lead SBDIP  
X
X
X
L
X
X
X
H
L
X
L
o
HCTS21K/  
Sample  
+25 C  
14 Lead Ceramic  
Flatpack  
X
X
L
L
H
H
H
H
o
HCTS21HMSR  
+25 C  
Die  
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518618  
File Number 3053.1  
http://www.intersil.com | Copyright © Intersil Corporation 1999  
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