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HCTS191D/SAMPLE

更新时间: 2024-11-01 22:09:35
品牌 Logo 应用领域
英特矽尔 - INTERSIL 计数器触发器逻辑集成电路
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10页 169K
描述
Radiation Hardened Synchronous 4-Bit Up/Down Counter

HCTS191D/SAMPLE 数据手册

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HCTS191MS  
Radiation Hardened  
Synchronous 4-Bit Up/Down Counter  
September 1995  
Features  
Pinouts  
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE  
(SBDIP) MIL-STD-1835 CDIP2-T16  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-  
Day (Typ)  
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s  
• Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse  
• Cosmic Ray Upset Immunity 2 x 10-9 Errors/Bit Day  
• Latch-Up Free Under Any Conditions  
• Fanout (Over Temperature Range)  
- Standard Outputs - 10 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• LSTTL Input Compatibility  
VCC  
P0  
P1  
Q1  
16  
15  
14  
13  
1
2
3
4
5
6
7
8
Q0  
CP  
CE  
RC  
U/D  
Q2  
12 TC  
PL  
11  
10 P2  
P3  
Q3  
GND  
9
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP4-F16  
TOP VIEW  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
• Input Current Levels Ii 5µA @ VOL, VOH  
VCC  
P0  
P1  
Q1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Description  
Q0  
CP  
RC  
TC  
PL  
The Intersil HCTS191MS is a Radiation Hardened asynchro-  
nously presettable 4 bit binary up/down synchronous counter.  
Presetting the counter to the number on the preset data inputs  
(P0 - P3) is accomplished by a low asynchronous parallel load  
input (PL). Counting occurs when PL is high, Count Enable (CE)  
is low, and the Up/Down (U/D) input is either low for up-counting  
or high for down-counting. The counter is incremented or decre-  
mented synchronously with the low-to-high transition of the clock.  
CE  
U/D  
Q2  
P2  
Q3  
P3  
GND  
When an overflow or underflow of the counter occurs, the  
Terminal Count output (TC), which is low during counting, goes  
high and remains high for one clock cycle. This output can be  
used for look-ahead carry in high speed cascading. The TC  
output also initiates the Ripple Clock output (RC) which, normally  
high, goes low and remains low for the low-level portion of the  
clock pulse. These counter can be cascaded using the Ripple  
Carry output.  
TRUTH TABLE  
FUNCTION  
PL  
H
CE  
L
U/D  
L
CP  
Count Up  
Count Down  
H
L
H
Asynchronous Preset  
No Change  
L
X
X
X
X
H
H
X
The HCTS191MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
H = High Level, L = Low Level, X = Immaterial  
= Transition from low to high  
NOTE: U/D or CE should be changed only when CLOCK (CP)  
is high.  
The HCTS191MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART NUMBER  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
16 Lead SBDIP  
o
o
HCTS191DMSR  
-55 C to +125 C  
o
o
HCTS191KMSR  
-55 C to +125 C  
16 Lead Ceramic Flatpack  
16 Lead SBDIP  
o
HCTS191D/Sample  
HCTS191K/Sample  
HCTS191HMSR  
+25 C  
o
+25 C  
Sample  
16 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518621  
File Number 2250.2  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
580  

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