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HCF4502BC1 PDF预览

HCF4502BC1

更新时间: 2024-11-03 22:31:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 268K
描述
STROBED HEX INVERTER/BUFFER

HCF4502BC1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83其他特性:WITH COMMON INHIBIT FOR ALL BITS
控制类型:ENABLE LOW系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:6
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/15 V
Prop。Delay @ Nom-Sup:380 ns传播延迟(tpd):270 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.965 mmBase Number Matches:1

HCF4502BC1 数据手册

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HCC/HCF4502B  
STROBED HEX INVERTER/BUFFER  
.
.
.
.
.
2 TTL-LOAD OUTPUT DRIVE CAPABILITY  
3-STATE OUTPUTS  
COMMON OUTPUT-DISABLE CONTROL  
INHIBIT CONTROL  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
EY  
F
.
.
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N°. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
M1  
C1  
Micro Package  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4502BF  
HCF4502BEY  
HCF4502BM1  
HCF4502BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4502B (extended temperature range) and  
HCF4502B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micro package. The HCC/HCF 4502B consists of  
six inverter-buffers with 3-state outputs. A logic ”1”  
on the OUTPUT DISABLE input produces a high-  
impedance state in all six outputs. This feature per-  
mits common busing of the outputs, thus simplifying  
systemdesign. A logic1” on the INHIBITinput swit-  
ches all six outputs to logic ”0” if the OUTPUT DIS-  
ABLE input is a logic ”0”. This device is capable of  
driving two standard TTL loads, which is equivalent  
to six times the JEDEC ”B” series IOL standard.  
June 1989  
1/11  

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