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HCF4502BEY PDF预览

HCF4502BEY

更新时间: 2024-11-23 22:31:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 268K
描述
STROBED HEX INVERTER/BUFFER

HCF4502BEY 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.31
Is Samacsys:N其他特性:WITH COMMON INHIBIT FOR ALL BITS
控制类型:ENABLE LOW系列:4000/14000/40000
JESD-30 代码:R-PDIP-T16JESD-609代码:e3
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:6功能数量:1
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):245电源:5/15 V
Prop。Delay @ Nom-Sup:380 ns传播延迟(tpd):380 ns
认证状态:Not Qualified座面最大高度:5.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):20 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

HCF4502BEY 数据手册

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HCC/HCF4502B  
STROBED HEX INVERTER/BUFFER  
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2 TTL-LOAD OUTPUT DRIVE CAPABILITY  
3-STATE OUTPUTS  
COMMON OUTPUT-DISABLE CONTROL  
INHIBIT CONTROL  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
EY  
F
.
.
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N°. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
M1  
C1  
Micro Package  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4502BF  
HCF4502BEY  
HCF4502BM1  
HCF4502BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4502B (extended temperature range) and  
HCF4502B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micro package. The HCC/HCF 4502B consists of  
six inverter-buffers with 3-state outputs. A logic ”1”  
on the OUTPUT DISABLE input produces a high-  
impedance state in all six outputs. This feature per-  
mits common busing of the outputs, thus simplifying  
systemdesign. A logic1” on the INHIBITinput swit-  
ches all six outputs to logic ”0” if the OUTPUT DIS-  
ABLE input is a logic ”0”. This device is capable of  
driving two standard TTL loads, which is equivalent  
to six times the JEDEC ”B” series IOL standard.  
June 1989  
1/11  

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