Datasheet > HCF4510B_02

HCF4510B_02

更新时间： 2024-09-16 04:42:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器
页数	文件大小	规格书
11页	485K
描述
PRESETTABLE BCD UP/DOWN COUNTER

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中文翻译

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数据手册

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HCF4510B_02 数据手册

HCF4510B

PRESETTABLE BCD UP/DOWN COUNTER

■

MEDIUM SPEED OPERATION :

8 MHz (Typ.) at 10V

SYNCHRONOUS INTERNAL CARRY

PROPAGATION

■

RESET AND PRESET CAPABILITY

STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

DIP

■

QUIESCENT CURRENT SPECIF. UP TO 20V

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT LEAKAGE CURRENT

ORDER CODES

PACKAGE

I = 100nA (MAX) AT V = 18V T = 25°C

TUBE

T & R

■

100% TESTED FOR QUIESCENT CURRENT

DIP

HCF4510BEY

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

a maximum of four clock pulses in the down mode.

If the CARRY IN input is held low, the counter

advances up or down on each positive going clock

DESCRIPTION

transition.

Synchronous

cascading

HCF4510B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP package.

accomplished by connecting all clock inputs in

parallel and connecting the CARRY OUT of a less

significant stage to the CARRY IN of a more

significant stage. HCF4510B can be cascaded in

the ripple mode by connecting all clock inputs in

parallel and connecting the CARRY OUT to the

clock of the next stage. If the UP/DOWN input

changes during a terminal count, the CARRY OUT

must be gated with the clock, and the UP/DOWN

input must change while the clock is high. This

method provides a clean clock signal to the

subsequent counting stage.

It is

PRESETTABLE BCD UP/DOWN

COUNTER consists of four synchronously

clocked D-type flip-flops (with a gating structure to

provide T-type flip-flop capability) connected as a

counter. This counter can be cleared by a high

level on the RESET line, and can be preset to any

binary number present on the jam inputs by a high

level on the PRESET ENABLE line. This device

will count out of non-BCD counter states in a

maximum of two clock pulses in the up mode and

PIN CONNECTION

September 2002

1/11

12 3 4 5 6 7...11

中文翻译

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