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HCF4510 PDF预览

HCF4510

更新时间: 2024-11-05 22:55:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
12页 138K
描述
PRESETTABLE UP/DOWN COUNTERS

HCF4510 数据手册

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HCF4510B  
HCF4516B  
PRESETTABLE UP/DOWN COUNTERS  
MEDIUM SPEED OPERATIONfCL =8MHz  
TYP.AT10V  
SYNCHRONOUS INTERNAL CARRY  
PROPAGATION  
RESETAND PRESET CAPABILITY  
QUIESCENTCURRENT SPECIFIED TO 15V  
5V,10V,AND15VPARAMETRIC RATINGS  
INPUTCURRENT OF 100nAAT 15VAND 25°C  
100%TESTED FOR QUIESCENT CURRENT  
DIP  
SOP  
ORDER CODES  
PACKAGE  
DIP  
TUBE  
T & R  
HCF45XXBEY  
HCF45XXBM1  
MEETS ALL REQUIREMENTS OF JEDEC  
TENTATIVE STANDARD No. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
SOP  
HCF45XXM013TR  
and a maximum of four clock pulses in the down  
mode. If the CARRY-IN input is held low, the  
counter advances up or down on each  
positive-going clock transition. Synchronous  
cascading is accomplished by connecting all  
clock inputs in parallel and connecting the  
CARRY-OUT of a less significant stage to the  
CARRY-IN of a more significant stage. The  
HCF4510B and HCF4516B can be loaded in the  
ripple mode by connecting the CARRY-OUT to  
the clock of the next stage. If the UP/DOWN input  
DESCRIPTION  
The HCF4510B and HCF4516B are monolithic  
integrated circuits available in 16-lead dual in-line  
plastic and plastic micro package. The  
HCF4510B Presettable BCD Up/Down Counter  
and the HCF4516B Presettable Binary Up/Down  
Counter consist of four synchronously clocked  
D-type flip-flops (with a gating structure to provide  
T-type flip-flop capability) connected as counters.  
These counters can be cleared by a high level on  
the RESET line, and can be preset to any binary  
number present on the jam inputs by a high level  
on the PRESET ENABLE line. The HCF4510B  
will count out of non-BCD counter states in a  
maximum of two clock pulses in the up mode,  
changes during  
a
terminal count, the  
CARRY-OUT must be gated with the clock, and  
the UP/DOWN input must change while the clock  
is high. This method provides a clean clock signal  
to the subsequentcounting stage.  
PIN CONNECTION  
1/12  
March 2000  

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