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HCF4099BC1 PDF预览

HCF4099BC1

更新时间: 2024-11-03 22:25:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路双倍数据速率
页数 文件大小 规格书
14页 305K
描述
8-BIT ADDRESSABLE LATCH

HCF4099BC1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
其他特性:1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH位数:1
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/15 V
Prop。Delay @ Nom-Sup:400 ns传播延迟(tpd):400 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:LOW LEVEL宽度:8.965 mm
Base Number Matches:1

HCF4099BC1 数据手册

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HCC/HCF4099B  
8-BIT ADDRESSABLE LATCH  
.
.
SERIAL DATA INPUT - ACTIVE PARALLEL  
OUTPUT  
STORAGE REGISTER CAPABILITY - MASTER  
CLEAR  
CAN FUNCTION AS DEMULTIPLEXER  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N°. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
EY  
F
.
Plastic Package  
Ceramic Frit Seal Package  
.
.
.
.
M1  
C1  
Micro Package  
Plastic Chip Carrier  
ORDER CODES :  
HCC4099BF  
HCF4099BM1  
HCF4099BEY  
HCF4099BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4099B (extended temperature range) and  
HCF4099B (intermediate temperature range) are  
monolithic integratedcircuits, available in16-lead dual  
in-line plastic or ceramic package and plastic micro  
package. The HCC/HCF4099B 8-bit addressable  
latchisaserial-input, parallel-output storage register  
that can perform a variety of functions. Data are in-  
putted to a particular bit in the latch when that bit is  
addressed (by means of inputs A0, A1, A2) and  
when WRITE DISABLE is at a low level. When  
WRITE DISABLE is high, data entry is inhibited ;  
however, all 8 outputs can be continuously read in-  
dependent of WRITE DISABLE and address inputs.  
A master RESET input is available, which resets all  
bits to a logic ”0” level when RESET and WRITE  
DISABLE are at a high level. When RESET is at a  
high level, and WRITE DISABLE is at a low level, the  
latch acts as a 1-of-8 demultiplexer ; the bit that is  
addressed has an active output which follows the  
data input, while all unaddressed bits are held to a  
logic ”0” level.  
September 1988  
1/14  

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