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HCF4027M013TR PDF预览

HCF4027M013TR

更新时间: 2024-10-27 04:56:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 218K
描述
DUAL J-K MASTER SLAVE FLIP-FLOP

HCF4027M013TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SO-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.27
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:3500000 Hz
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:5/15 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):20 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:12 MHz
Base Number Matches:1

HCF4027M013TR 数据手册

 浏览型号HCF4027M013TR的Datasheet PDF文件第2页浏览型号HCF4027M013TR的Datasheet PDF文件第3页浏览型号HCF4027M013TR的Datasheet PDF文件第4页浏览型号HCF4027M013TR的Datasheet PDF文件第5页浏览型号HCF4027M013TR的Datasheet PDF文件第6页浏览型号HCF4027M013TR的Datasheet PDF文件第7页 
HCF4027B  
DUAL J-K MASTER SLAVE FLIP-FLOP  
SET RESET CAPABILITY  
STATIC FLIP-FLOP OPERATION - RETAINS  
STATE INDEFINETELY WITH CLOCK LEVEL  
EITHER "HIGH" OR "LOW"  
MEDIUM-SPEED OPERATION - 16MHz  
(Typ. clock toggle rate at 10V)  
QUIESCENT CURRENT SPECIFIED UP TO  
20V  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT LEAKAGE CURRENT  
DIP  
SOP  
ORDER CODES  
PACKAGE  
TUBE  
T & R  
DIP  
HCF4027BEY  
HCF4027BM1  
I = 100nA (MAX) AT V = 18V T = 25°C  
I
DD  
A
SOP  
HCF4027M013TR  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALL REQUIREMENTS OF JEDEC  
JESD13B " STANDARD SPECIFICATIONS  
FOR DESCRIPTION OF B SERIES CMOS  
DEVICES"  
signals. Buffered Q and Q signals are provided as  
outputs. This input-output arrangement provides  
for compatible operation with the HCF4013B dual  
D type flip-flop.  
This device is useful in performing control,  
register, and toggle functions. Logic levels present  
at the J and K inputs, along with internal  
self-steering, control the state of each flip-flop;  
changes in the flip-flop state are synchronous with  
the positive-going transition of the clock pulse. Set  
and Reset functions are independent of the clock  
and are initiated when a high level signal is  
present at either the Set or Reset input.  
DESCRIPTION  
HCF4027B is a monolithic integrated circuit  
fabricated in Metal Oxide Semiconductor  
technology available in DIP and SOP packages.  
HCF4027B is a single monolithic chip integrated  
circuit  
containing  
two  
J-K  
identical  
master-slave  
complementary-symmetry  
flip-flops. Each flip-flop has provisions for  
individual J, K, Set, Reset, and Clock input  
PIN CONNECTION  
September 2002  
1/9  

HCF4027M013TR 替代型号

型号 品牌 替代类型 描述 数据表
HEF4027BT,652 NXP

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CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

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