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HCF4029 PDF预览

HCF4029

更新时间: 2024-10-26 23:54:55
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
12页 477K
描述
PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

HCF4029 数据手册

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HCF4029B  
PRESETTABLE UP/DOWN COUNTER  
BINARY OR BCD DECADE  
MEDIUM SPEED OPERATION : 8MHz (Typ.)  
at C = 50pF and V - V = 10V  
L
DD  
SS  
MULTI-PACKAGE PARALLEL CLOCKING  
FOR SYNCHRONOUS HIGH SPEED  
OUTPUT RESPONSE OR RIPPLE  
CLOCKING FOR SLOW CLOCK INPUT RISE  
AND FALL TIMES  
DIP  
SOP  
"PRESET ENABLE" AND INDIVIDUAL "JAM"  
INPUTS PROVIDED  
BINARY OR DECADE UP/DOWN  
COUNTING  
BCD OUTPUTS IN DECADE MODE  
QUIESCENT CURRENT SPECIF. UP TO 20V  
ORDER CODES  
PACKAGE  
TUBE  
T & R  
DIP  
HCF4029BEY  
HCF4029BM1  
SOP  
HCF4029M013TR  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
INPUT LEAKAGE CURRENT  
inputs consist of a single CLOCK, CARRY IN  
(CLOCK ENABLE), BINARY/DECADE, UP/  
DOWN, PRESET ENABLE, and four individual  
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT  
signal are provided as outputs. A high PRESET  
ENABLE signal allows information on the JAM  
INPUTS to preset the counter to any state  
asynchronously with the clock. A low on each JAM  
line, when the PRESET-ENABLE signal is high,  
resets the counter to its zero count. The counter  
advances one count at the positive transition of  
the clock when the CARRY-IN and PRESET  
ENABLE signals are low. Advancement is  
inhibited when the CARRY-IN or PRESET  
ENABLE signals are high. The CARRY-OUT  
I = 100nA (MAX) AT V = 18V T = 25°C  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALL REQUIREMENTS OF JEDEC  
JESD13B "STANDARD SPECIFICATIONS  
FOR DESCRIPTION OF B SERIES CMOS  
DEVICES"  
I
DD  
A
DESCRIPTION  
HCF4029B is a monolithic integrated circuit  
fabricated in Metal Oxide Semiconductor  
technology available in DIP and SOP packages.  
HCF4029B consists of a four stage binary or  
BCD-decade up/down counter with provisions for  
look ahead carry in both counting modes. The  
PIN CONNECTION  
September 2002  
1/12  

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