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GVT7164C18Q-7 PDF预览

GVT7164C18Q-7

更新时间: 2024-11-01 02:53:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 脉冲
页数 文件大小 规格书
12页 161K
描述
64K x 18 Synchronous Burst RAM Pipelined Output

GVT7164C18Q-7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:7 ns
其他特性:PIPELINED ARCHITECTUREI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:1179648 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.7X.9封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:3.4 mm
最大待机电流:0.002 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.27 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

GVT7164C18Q-7 数据手册

 浏览型号GVT7164C18Q-7的Datasheet PDF文件第2页浏览型号GVT7164C18Q-7的Datasheet PDF文件第3页浏览型号GVT7164C18Q-7的Datasheet PDF文件第4页浏览型号GVT7164C18Q-7的Datasheet PDF文件第5页浏览型号GVT7164C18Q-7的Datasheet PDF文件第6页浏览型号GVT7164C18Q-7的Datasheet PDF文件第7页 
298A  
CY7C1298A/  
GVT7164C18  
64K x 18 Synchronous Burst RAM  
Pipelined Output  
The CY7C1298A/GVT7164C18 SRAM integrates 65536x18  
SRAM cells with advanced synchronous peripheral circuitry  
and a 2-bit counter for internal burst operation. All synchro-  
nous inputs are gated by registers controlled by a posi-  
tive-edge-triggered Clock input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Chip Enable (CE), depth-expansion Chip Enables (CE2 and  
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-  
ables (WEL, WEH, and BWE), and Global Write (GW).  
Features  
• Fast access times: 5, 6, 7, and 8 ns  
• Fast clock speed: 100, 83, 66, and 50 MHz  
• Provide high-performance 3-1-1-1 access rate  
• Fast OE access times: 5 and 6 ns  
• Optimal for performance (two cycle chip deselect,  
depth expansion without wait state)  
• Single +3.3V –5 to +10% power supply  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSSQ at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (Q), enabled  
by OE, are also asynchronous.  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the burst advance pin (ADV).  
• Three chip enables for depth expansion and address  
pipeline  
• Address, control, input, and output pipeline registers  
• Internally self-timed Write Cycle  
• Write pass-through capability  
• Burst control pins (interleaved or linear burst se-  
quence)  
• Automatic power-down for portable applications  
• High-density, high-speed packages  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the write control inputs. Indi-  
vidual byte write allows individual byte to be written. WEL con-  
trols DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and  
DQP2. WEL and WEH can be active only with BWE being  
LOW. GW being LOW causes all bytes to be written. This de-  
vice also incorporates Write pass-through capability and pipe-  
lined enable circuit for better system performance.  
• Low capacitive bus loading  
• High 30-pF output drive capability at rated access time  
The CY7C1298A/GVT7164C18 operates from a +3.3V power  
supply. All inputs and outputs are TTL-compatible. The device  
is ideally suited for 486, Pentium®, 680x0, and PowerPC™  
systems and for systems that are benefited from a wide syn-  
chronous data bus.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced dou-  
ble-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
Selection Guide  
7C1298A-100  
7164C18-5  
7C1298A-83  
7164C18-6  
7C1298A-66  
7164C18-7  
7C1298A-50  
7164C18-8  
Maximum Access Time (ns)  
5
360  
2
6
315  
2
7
270  
2
8
225  
2
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Pentium is a registered trademark of Intel Corporation.  
PowerPC is a trademark of International Business Machines, Inc.  
Cypress Semiconductor Corporation  
Document #: 38-05194 Rev. *A  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised January 19, 2003  

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