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GVT7164T18T-7 PDF预览

GVT7164T18T-7

更新时间: 2024-11-01 15:33:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
13页 129K
描述
Cache Tag SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

GVT7164T18T-7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:4 ns
其他特性:PIPELINED ARCHITECTUREI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:1179648 bit
内存集成电路类型:CACHE TAG SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.01 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

GVT7164T18T-7 数据手册

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ADVANCE INFORMATION  
GVT7164T18  
64K X 18 SYNCHRONOUS TAG SRAM  
GALVANTECH, INC.  
SYNCHRONOUS  
CACHE TAG SRAM  
PIPELINED OUTPUT  
64K x 18 SRAM  
+3.3V SUPPLY WITH CLOCKED  
REGISTERED INPUTS  
FEATURES  
GENERAL DESCRIPTION  
Fast match times: 4.5, 5.0, 6.0, and 7.0ns  
Fast clock speed: 133, 100, 83, and 75 MHz  
Fast OE# access times: 4.5ns and 5.0ns  
Pipelined data comparator  
Data input register load control by DEN#  
3.3V -5% and +10% power supply  
The Galvantech Synchronous SRAM family employs  
high-speed, low power CMOS designs using advanced triple-  
layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
The GVT7164T18 SRAM integrates 65,536 x 18 SRAM  
cells with advanced synchronous peripheral circuitry and a  
18-bit comparator for tag compare operation. All synchronous  
inputs are gated by registers controlled by a positive-edge-  
triggered clock input (CLK). The synchronous inputs include  
all addresses, all data inputs, depth-expansion chip enables  
(CE# and CE1), write enable (WE#), and data input enable  
(DEN#).  
Asynchronous inputs include the output enable (OE#)  
and the match output enable (MOE#). The data outputs (Q)  
and match output (MATCH), enabled by OE# and MOE#  
respectively, are also asynchronous.  
Data inputs are registered with data input enable (DEN#)  
and chip enable pins (CE#, CE1). The outputs of the data  
input registers are compared with data in the memory array  
and a match signal is generated. The match output is gated  
into a pipeline register and released to the match output pin at  
the next rising edge of clock (CLK).  
5V tolerant inputs except I/O’s  
Clamp diodes to VSS at all inputs and outputs  
Common data inputs and data outputs  
Two chip enables for depth expansion  
Address, data and control registers  
Internally self-timed WRITE CYCLE  
Automatic power-down for portable applications  
Low profile 119 lead, 14mm x 22mm BGA (Ball Grid  
Array) and 100 pin TQFP packages  
OPTIONS  
MARKING  
Timing  
4.5ns access/7.5ns cycle  
5.0ns access/10ns cycle  
6.0ns access/12ns cycle  
7.0ns access/13.3ns cycle  
-4  
-5  
-6  
-7  
Packages  
The GVT7164T18 operates from a +3.3V power supply.  
All inputs and outputs are LVTTL compatible. The device is  
ideally suited for address tag RAM for up to 2 MB secondary  
cache.  
119-lead BGA  
100-pin TQFP  
B
T
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051  
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com  
Rev. 11/97  
Galvantech, Inc. reserves the right to change  
products or specifications without notice.  

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