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GVT7264A16J-12L PDF预览

GVT7264A16J-12L

更新时间: 2024-11-25 20:23:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 81K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44

GVT7264A16J-12L 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:SOJ-44
Reach Compliance Code:compliant风险等级:5.89
Is Samacsys:N最长访问时间:12 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J44
JESD-609代码:e0长度:28.6 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:3.76 mm
最大待机电流:0.0004 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

GVT7264A16J-12L 数据手册

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GVT7264A16  
REVOLUTIONARY PINOUT 64K X 16  
GALVANTECH, INC.  
ASYNCHRONOUS  
SRAM  
64K x 16 SRAM  
WITH SINGLE CHIP ENABLE  
REVOLUTIONARY PINOUT  
FEATURES  
GENERAL DESCRIPTIO N  
Fast access times: 10, 12, 15and 20ns  
Fast OE# access times: 5, 6, 7 and 8ns  
Single +5V +10% power supply  
Fully static -- no clock or timing strobes necessary  
All inputs and outputs are TTL-compatible  
Three state outputs  
Center power and ground pins for greater noise immunity  
Easy memory expansion with CE# and OE# options  
Automatic CE# power down  
High-performance, low-power consumption, CMOS  
double-poly, double-metal process  
The GVT7264A16 is organized as a 65,536 x 16 SRAM  
using a four-transistor memory cell with a high performance,  
silicon gate, low-power CMOS process. Galvantech SRAMs  
are fabricated using double-layer polysilicon, double-layer  
metal technology.  
This device offers center power and ground pins for  
improved performance and noise immunity. Static design  
eliminates the need for external clocks or timing strobes. For  
increased system flexibility and eliminating bus contention  
problems, this device offers chip enable (CE#), separate byte  
enable controls (BLE# and BHE#) and output enable (OE#)  
with this organization.  
Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil  
TSOP  
The device offers a low power standby mode when chip  
is not selected. This allows system designers to meet low  
standby power requirements.  
OPTIONS  
MARKING  
Timing  
10ns access  
12ns access  
15ns access  
20ns access  
-10  
-12  
-15  
-20  
PIN ASSIGNMENT  
44-Pin SOJ  
44-Pin TSOP  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A4  
A3  
A5  
A6  
Packages  
44-pin SOJ (400 mil)  
44-pin TSOP (400 mil)  
2
J
TS  
3
A2  
A1  
A0  
A7  
4
OE#  
BHE#  
BLE#  
DQ16  
DQ15  
DQ14  
DQ13  
VSS  
VCC  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
5
Power consumption  
Standard  
Low  
6
CE#  
DQ1  
DQ2  
DQ3  
DQ4  
VCC  
VSS  
DQ5  
DQ6  
DQ7  
DQ8  
WE#  
A15  
A14  
A13  
A12  
NC  
None  
L
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Temperature  
Commercial  
Industrial  
None (0°C to 70°C)  
I
(-40°C to 85°C)  
A8  
A9  
A10  
A11  
NC  
Galvantech, Inc. reserves the right to chaneg  
products or specifications without notic.e  
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051  
Tel (408) 566-0688 Fax (408) 566-0699 Web Site: http://www.galvantech.com  
Rev. 1/99  

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