Datasheet > 存储 > SRAM> GVT71256C36B-4.4

GVT71256C36B-4.4

更新时间： 2024-02-08 20:59:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
27页	308K
描述
256K x 36/512K x 18 Pipelined SRAM

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中文翻译

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技术参数
数据手册

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GVT71256C36B-4.4 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数：	119	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	最长访问时间：	2.5 ns
最大时钟频率 (fCLK)：	225 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
功能数量：	1	端子数量：	119
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA119,7X17,50
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	2.4 mm	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.57 mA	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GVT71256C36B-4.4 数据手册

CY7C1366A/GVT71256C36

CY7C1367A/GVT71512C18

256K x 36/512K x 18 Pipelined SRAM

and a 2-bit counter for internal burst operation. All synchro-

Features

nous inputs are gated by registers controlled by

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and

150 MHz

• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimalforperformance(twocyclechipdeselect,depth

expansion without wait state)

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelin-

ing Chip Enable (CE), depth-expansion Chip Enables (CE

and CE ), Burst Control Inputs (ADSC, ADSP, and ADV), Write

Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write

(GW). However, the CE Chip Enable input is only available for

the TA(GVTI)/A(CY) package version.

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

• Clamp diodes to V at all inputs and outputs

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

three chip enables for TA(GVTI)/A(CY) package version

and two chip enables for B(GVTI)/BG(CY) and

T(GVTI)/AJ(CY) package versions

• Address pipeline capability

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide, as controlled by the write control inputs.

Individual byte write allows an individual byte to be written.

BWa controls DQa. BWb controls DQb. BWc controls DQc.

BWd controls DQd. BWa, BWb, BWc, and BWd can be active

only with BWE being LOW. GW being LOW causes all bytes

to be written. The x18 version only has 18 data inputs/outputs

(DQa and DQb) along with BWa and BWb (no BWc, BWd,

DQc, and DQd).

For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-

sions, four pins are used to implement JTAG test capabilities:

Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),

and Test Data-Out (TDO). The JTAG circuitry is used to serially

shift data to and from the device. JTAG inputs use

LVTTL/LVCMOS levels to shift data during this testing mode of

operation. The TA package version does not offer the JTAG

capability.

• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high valued

resistors.

The

CY7C1366A/GVT71256C36

and

CY7C1367A/

GVT71512C18 operate from a +3.3V power supply. All inputs

and outputs are LVTTL compatible.

The

CY7C1366A/GVT71256C36

and

CY7C1367A/

GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x

18 SRAM cells with advanced synchronous peripheral circuitry

Selection Guide

7C1366A-225/

7C1366A-200/

71256C36-5

7C1367A-200/

71512C18-5

7C1366A-166/

71256C36-6

7C1367A-166/

71512C18-6

7C1366A-150/

71256C36-6.7

7C1367A-150/

71512C18-6.7

71256C36-4.4

7C1367A-225/

71512C18-4.4

Maximum Access Time (ns)

2.5

570

3.0

510

3.5

425

3.5

380

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

June 12, 2001

12 3 4 5 6 7...27

中文翻译

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与GVT71256C36B-4.4相关器件

型号	品牌	获取价格	描述	数据表
GVT71256C36B-5	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36B-5I	CYPRESS	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256C36B-6	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36B-6.7	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36B-6.7I	CYPRESS	获取价格	Cache SRAM, 256KX36, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
GVT71256C36T-4.4	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36T-5	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36T-5I	CYPRESS	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256C36T-6	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
GVT71256C36T-6.7	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM

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