CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Synchronous
Pipelined SRAM
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
Features
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
and
a 2-bit counter for internal burst operation. All
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150
MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect,
depth expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE3), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE3 Chip Enable input is only available
for the TA(GVTI)/A(CY) package version.
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ
mode or CE select.
• JTAG boundary scan for B/BG and T/AJ package
version
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package
versions, four pins are used to implement JTAG test capabil-
ities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock
(TCK), and Test Data-Out (TDO). The JTAG circuitry is used
to serially shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode
of operation. The TA package version does not offer the JTAG
capability.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The
CY7C1366A/GVT71256C36
and
CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
Unit
ns
Maximum Access Time
2.5
570
10
3.0
510
10
3.5
425
10
3.5
380
10
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05264 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 17, 2003
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