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Datasheet > GTL2003BQ,118
GTL2003BQ,118 PDF预览

GTL2003BQ,118

更新时间： 2024-11-26 20:57:47
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管接口集成电路
页数 文件大小 规格书
24页 399K
描述
GTL2003 - 8-bit bidirectional low voltage translator QFN 20-Pin

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GTL2003BQ,118 技术参数

Source Url Status Check Date：2013-06-14 00:00:00生命周期：Obsolete
零件包装代码：QFN包装说明：2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20
针数：20Reach Compliance Code：unknown
风险等级：5.17接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-N20JESD-609代码：e4
长度：3 mm湿度敏感等级：1
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VSON
封装等效代码：LCC20,.1X.18,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：2.5,3.3 V认证状态：Not Qualified
座面最大高度：1 mm子类别：Other Interface ICs
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：2.64 V
电源电压1-分钟：2.36 V电源电压1-Nom：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：NO LEAD
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：2.5 mm
Base Number Matches：1

GTL2003BQ,118 数据手册

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GTL2003  
8-bit bidirectional low voltage translator  
Rev. 2 — 3 July 2012  
Product data sheet  
1. General description  
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide  
high-speed voltage translation with low ON-state resistance and minimal propagation  
delay. The GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common  
gate (GREF) and a reference transistor (SREF and DREF). The device allows  
bidirectional voltage translations between 0.8 V and 5.0 V without use of a direction pin.  
Voltage translation below 0.8 V can be achieved when properly biased. For more  
information, refer to application note AN11127 (Ref. 1).  
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance  
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn  
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by  
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VDD1  
by the pull-up resistors. This functionality allows a seamless translation between higher  
and lower voltages selected by the user, without the need for directional control.  
All transistors have the same electrical characteristics and there is minimal deviation from  
one output to another in voltage or propagation delay. This is a benefit over discrete  
transistor voltage translation solutions, since the fabrication of the transistors is  
symmetrical. Because all transistors in the device are identical, SREF and DREF can be  
located on any of the other eight matched Sn/Dn transistors, allowing for easier board  
layout. The translator's transistors provide excellent ESD protection to lower voltage  
devices and at the same time protect less ESD-resistant devices.  
2. Features and benefits  
8-bit bidirectional low voltage translator  
Allows voltage level translation between 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,  
3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and  
5 V CMOS levels  
Provides bidirectional voltage translation with no direction pin  
Low 6.5 ON-state resistance (Ron) between input and output pins (Sn/Dn)  
Supports hot insertion  
No power supply required: will not latch up  
5 V tolerant inputs  
Low standby current  
Flow-through pinout for ease of printed-circuit board trace routing  
ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per  
JESD22-C101  
Packages offered: TSSOP20, DHVQFN20  
 
 
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