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GTL2003PW PDF预览

GTL2003PW

更新时间： 2024-11-26 03:40:03
品牌 Logo 应用领域
恩智浦 - NXP 转换器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
19页 113K
描述
8-bit bidirectional low voltage translator

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中文翻译

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GTL2003PW 技术参数

是否Rohs认证： 符合生命周期：Not Recommended
零件包装代码：TSSOP包装说明：TSSOP,
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.09
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm湿度敏感等级：1
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：2.64 V电源电压1-分钟：2.36 V
电源电压1-Nom：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

GTL2003PW 数据手册

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GTL2003  
8-bit bidirectional low voltage translator  
Rev. 01 — 27 July 2007  
Product data sheet  
1. General description  
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide  
high-speed voltage translation with low ON-state resistance and minimal propagation  
delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate  
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional  
voltage translations between 1.0 V and 5.0 V without use of a direction pin.  
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance  
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn  
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by  
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by  
the pull-up resistors. This functionality allows a seamless translation between higher and  
lower voltages selected by the user, without the need for directional control.  
All transistors have the same electrical characteristics and there is minimal deviation from  
one output to another in voltage or propagation delay. This is a benefit over discrete  
transistor voltage translation solutions, since the fabrication of the transistors is  
symmetrical. Because all transistors in the device are identical, SREF and DREF can be  
located on any of the other eight matched Sn/Dn transistors, allowing for easier board  
layout. The translator's transistors provide excellent ESD protection to lower voltage  
devices and at the same time protect less ESD-resistant devices.  
2. Features  
I 8-bit bidirectional low voltage translator  
I Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V  
buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels  
I Provides bidirectional voltage translation with no direction pin  
I Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)  
I Supports hot insertion  
I No power supply required: will not latch up  
I 5 V tolerant inputs  
I Low standby current  
I Flow-through pinout for ease of printed-circuit board trace routing  
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-C101  
I Packages offered: TSSOP20, DHVQFN20  
1234567...19

中文翻译

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GTL2003PW 替代型号

型号 品牌 替代类型 描述 数据表
GTL2003PW,118 NXP

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