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GS88118CGT-2300IT PDF预览

GS88118CGT-2300IT

更新时间： 2024-11-19 06:17:59
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 524K
描述
Cache SRAM, 512KX18, CMOS, ROHS COMPLIANT, TQFP-100

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GS88118CGT-2300IT 技术参数

生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.63
其他特性：ALSO OPERATES WITH 2.3V TO 2.7V SUPPLY, FLOW THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码：R-XQFP-G100
长度：20 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
封装主体材料：UNSPECIFIED封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：SERIAL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mm

GS88118CGT-2300IT 数据手册

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GS88118/32/36C(T/D)-xxxI  
333 MHz–150 MHz  
512K x 18, 256K x 32, 256K x 36  
9Mb Sync Burst SRAMs  
100-pin TQFP & 165-bump BGA  
Industrial Temp  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Flow Through/Pipeline Reads  
Features  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
SCD Pipelined Reads  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP and 165-bump BGA  
packages  
• RoHS-compliant 100-lead TQFP and 165-bump BGA  
packages available  
The GS88118C(T/D)/GS88132C(88132CT/D)/GS88136C(T/  
D) is a SCD (Single Cycle Deselect) pipelined synchronous  
SRAM. DCD (Dual Cycle Deselect) versions are also  
available. SCD SRAMs pipeline deselect commands one stage  
less than read commands. SCD RAMs begin turning off their  
outputs immediately after the deselect command has been  
captured in the input registers.  
Functional Description  
Byte Write and Global Write  
Applications  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D) is a  
9,437,184-bit high performance synchronous SRAM with a 2-  
bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enable (E1, E2), address burst  
control inputs (ADSP, ADSC, ADV) and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Core and Interface Voltages  
The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D)  
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V  
and 2.5 V compatible. Separate output power (V  
) pins are  
DDQ  
used to decouple output noise from the internal circuits and are  
3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-333I  
-300I  
-250I  
-200I  
-150I  
Unit  
tKQ  
2.5  
3.0  
2.5  
3.3  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
260  
300  
245  
280  
215  
245  
190  
215  
160  
180  
mA  
mA  
tKQ  
4.5  
4.5  
5.0  
5.0  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
200  
225  
185  
210  
180  
200  
160  
180  
148  
165  
mA  
mA  
Rev: 1.04a 10/2012  
1/35  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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