Datasheet > GS88118CGT-333

GS88118CGT-333

更新时间： 2024-11-18 21:01:59

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
35页	526K
描述
Cache SRAM, 512KX18, CMOS, ROHS COMPLIANT, TQFP-100

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GS88118CGT-333 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
Factory Lead Time：	8 weeks	风险等级：	5.28
其他特性：	ALSO OPERATES WITH 2.3V TO 2.7V SUPPLY, FLOW THROUGH OR PIPELINED ARCHITECTURE	JESD-30 代码：	R-XQFP-G100
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX18
封装主体材料：	UNSPECIFIED	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS88118CGT-333 数据手册

GS88118/32/36C(T/D)-xxx

333 MHz–150 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

100-pin TQFP & 165-bump BGA

Commercial Temp

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

• RoHS-compliant 100-lead TQFP and 165-bump BGA

packages available

The GS88118C(T/D)/GS88132C(88132CT/D)/GS88136C(T/

D) is a SCD (Single Cycle Deselect) pipelined synchronous

SRAM. DCD (Dual Cycle Deselect) versions are also

available. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers.

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D) is a

9,437,184-bit high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Core and Interface Voltages

The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D)

operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V

and 2.5 V compatible. Separate output power (V

) pins are

DDQ

used to decouple output noise from the internal circuits and are

3.3 V and 2.5 V compatible.

Parameter Synopsis

-333

-300

-250

-200

-150

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

240

280

225

260

195

225

170

195

140

160

t_KQ

4.5

5.0

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

180

205

165

190

160

180

140

160

128

145

Rev: 1.04a 10/2012

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

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与GS88118CGT-333相关器件

型号	品牌	获取价格	描述	数据表
GS88118CGT-333I	GSI	获取价格	100 TQFP
GS88118CT-150IV	GSI	获取价格	Cache SRAM, 512KX8, 7.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-150IVT	GSI	获取价格	Cache SRAM, 512KX8, 7.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-200IV	GSI	获取价格	Cache SRAM, 512KX8, 6.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-200IVT	GSI	获取价格	Cache SRAM, 512KX8, 6.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-2300I	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-2300IT	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-250IVT	GSI	获取价格	Cache SRAM, 512KX8, 5.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-250T	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-333	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100

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