Datasheet > GS88118CT-150IV

GS88118CT-150IV

更新时间： 2024-11-22 09:17:27

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
35页	506K
描述
Cache SRAM, 512KX8, 7.5ns, CMOS, PQFP100, TQFP-100

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技术参数
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GS88118CT-150IV 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.28
最长访问时间：	7.5 ns	其他特性：	ALSO OPERATES AT 2.5V
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	4194304 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	8	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm

GS88118CT-150IV 数据手册

GS88118/32/36C(T/D)-xxxIV

250 MHz–150 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

100-pin TQFP & 165-bump BGA

Industrial Temp

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

Flow Through/Pipeline Reads

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

• RoHS-compliant 100-lead TQFP and 165-bump BGA

packages available

The GS88118/32/36C(T/D)-xxxIV is a SCD (Single Cycle

Deselect) pipelined synchronous SRAM. DCD (Dual Cycle

Deselect) versions are also available. SCD SRAMs pipeline

deselect commands one stage less than read commands. SCD

RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers.

Functional Description

Applications

The GS88118/32/36C(T/D)-xxxIV is a 9,437,184-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88118/32/36C(T/D)-xxxIV operates on a 1.8 V or 2.5

V power supply. All input are 1.8 V and 2.5 V compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuits and are 1.8 V and 2.5 V

compatible.

Parameter Synopsis

-250I

-200I

-150I

Unit

t_KQ

3.0

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

195

220

170

185

145

165

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

155

175

135

160

133

145

Rev: 1.04 6/2012

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

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与GS88118CT-150IV相关器件

型号	品牌	获取价格	描述	数据表
GS88118CT-150IVT	GSI	获取价格	Cache SRAM, 512KX8, 7.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-200IV	GSI	获取价格	Cache SRAM, 512KX8, 6.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-200IVT	GSI	获取价格	Cache SRAM, 512KX8, 6.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-2300I	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-2300IT	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-250IVT	GSI	获取价格	Cache SRAM, 512KX8, 5.5ns, CMOS, PQFP100, TQFP-100
GS88118CT-250T	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-333	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118CT-333T	GSI	获取价格	Cache SRAM, 512KX18, CMOS, TQFP-100
GS88118GT-100	GSI	获取价格	Cache SRAM, 512KX18, 12ns, CMOS, PQFP100, TQFP-100

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