Datasheet > GS88118GT-11.5T

GS88118GT-11.5T

更新时间： 2024-11-21 21:08:15

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
33页	463K
描述
Cache SRAM, 512KX18, 11.5ns, CMOS, PQFP100, TQFP-100

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技术参数
数据手册

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GS88118GT-11.5T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.65
最长访问时间：	11.5 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	PURE MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS88118GT-11.5T 数据手册

Preliminary

GS88118/36T-11/11.5/100/80/66

100-Pin TQFP

Commercial Temp

Industrial Temp

100 MHz–66 MHz

3.3 V V_DD

3.3 V and 2.5 V I/O

512K x 18, 256K x 36 ByteSafe™

8Mb Sync Burst SRAMs

counter may be configured to count in either linear or

1.11 9/2000Features

• FT pin for user-configurable flow through or pipelined

operation

• Single Cycle Deselect (SCD) Operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• 3.3 V +10%/–5% core power supply

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 100-lead TQFP package

SCD Pipelined Reads

The GS88118//36T is a SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

-11

-11.5

10 ns

-100

-80

-66

Byte Write and Global Write

Pipeline tCycle 10 ns

10 ns 12.5 ns 15 ns

3-1-1-1

4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns

225 mA 225 mA 225 mA 200 mA 185 mA

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

Flow

Through

2-1-1-1

11 ns 11.5 ns 12 ns

15 ns 15 ns 15 ns

180 mA 180 mA 180 mA 175 mA 165 mA

14 ns

15 ns

18 ns

20 ns

tCycle

ByteSafe™ Parity Functions

The GS88118/36T features ByteSafe data security functions.

See detailed discussion following.

Functional Description

Sleep Mode

Applications

Low power (Sleep mode) is attained through the assertion

(high) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

The GS88118//36T is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Core and Interface Voltages

The GS88118//36T operates on a 3.3 V power supply, and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

Controls

from the internal circuit.

Addresses, data I/Os, chip enables (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.11 9/2000

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...33

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与GS88118GT-11.5T相关器件

型号	品牌	获取价格	描述	数据表
GS88118GT-11T	GSI	获取价格	Cache SRAM, 512KX18, 11ns, CMOS, PQFP100, TQFP-100
GS88118GT-66I	GSI	获取价格	暂无描述
GS88118GT-66IT	GSI	获取价格	Cache SRAM, 512KX18, 18ns, CMOS, PQFP100, TQFP-100
GS88118GT-80I	GSI	获取价格	Cache SRAM, 512KX18, 14ns, CMOS, PQFP100, TQFP-100
GS88118GT-80T	GSI	获取价格	Cache SRAM, 512KX18, 14ns, CMOS, PQFP100, TQFP-100
GS88118T	GSI	获取价格	512K x 18, 256K x 36 ByteSafe⑩ 8Mb Sync Burst
GS88118T-100	GSI	获取价格	512K x 18, 256K x 36 ByteSafe⑩ 8Mb Sync Burst
GS88118T-100I	GSI	获取价格	512K x 18, 256K x 36 ByteSafe⑩ 8Mb Sync Burst
GS88118T-100IT	GSI	获取价格	Cache SRAM, 512KX18, 12ns, CMOS, PQFP100, TQFP-100
GS88118T-100T	GSI	获取价格	Cache SRAM, 512KX18, 12ns, CMOS, PQFP100, TQFP-100

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