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GS8662Q08GE-278I PDF预览

GS8662Q08GE-278I

更新时间: 2024-11-13 05:19:55
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
34页 1516K
描述
Standard SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8662Q08GE-278I 数据手册

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GS8662Q08/09/18/36E-278/250/200/167  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
278 MHz–167 MHz  
72Mb SigmaQuad-II  
Burst of 2 SRAM  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
Clocking and Addressing Schemes  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are indeendent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer. The device also allos the user to manipulate the  
output register clock inputs quasi independently with the C and  
C clock inputs. C and C are also independent single-ended  
clock inputs, not differential inputs. If the C clocks are tied  
high, the K clocks are routed internally to fire the output  
registers instead.  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and  
future 144Mb devices  
Each internal rad and write operation in a SigmaQuad-II B2  
RAM is two times wider than the device I/O bus. An input data  
bus de-multiplexer is used to accumulate incoming data before  
it is simuaneously written to the memory array. An output  
data multiplexer is used to capture the data produced from a  
single memory array read and then route it to the appropriate  
output drivers as needed. Therefore the address field of a  
SigmaQuad-II B2 RAM is always one address pin less than the  
advertised index depth (e.g., the 8M x 8 has an 4M addressable  
index).  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
SigmaQuadFamily Overview  
The GSQ8662Q08/09/18/36E are built in compliance with  
the SigmaQuad-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs  
are just one element in a family of low power, low voltage  
HSTL I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking systems.  
Parameter Synopsis  
-278  
3.6 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
-200  
5.0 ns  
0.45 ns  
-167  
tKHKH  
tKHQV  
6.0 ns  
0.5 ns  
.
Rev: 1.09a 11/2011  
1/34  
© 2005, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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