GS8640Z18GT-250IVT

更新时间： 2024-11-13 13:00:43

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
25页	1035K
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GS8640Z18GT-250IVT 数据手册

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Product Preview

GS8640Z18/36T-300/250/200/167

300 MHz–167 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS8640Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, meaning that in addition to the rising edge

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8640Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

Parameter Synopsis

-300

-250

-200

-167

Unit

2.3

3.3

2.5

4.0

3.0

5.0

3.5

6.0

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

400

480

340

410

290

350

260

305

5.5

6.5

7.5

8.0

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

285

330

245

280

220

250

210

240

*All GSI Technology packages are at least 5/6 RoHS compliant.

Packages listed with the additional “G” designator are 6/6 RoHS compliant.

Rev: 1.01 1/2006

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...25

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与GS8640Z18GT-250IVT相关器件

型号	品牌	获取价格	描述	数据表
GS8640Z18GT-250T	GSI	获取价格	ZBT SRAM, 4MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8640Z18GT-250V	GSI	获取价格	72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18GT-250VT	GSI	获取价格	ZBT SRAM, 4MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8640Z18GT-300	GSI	获取价格	72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18GT-300I	GSI	获取价格	100 TQFP
GS8640Z18GT-300IT	GSI	获取价格	暂无描述
GS8640Z18RT-250M	GSI	获取价格	100 TQFP
GS8640Z18RT-333M	GSI	获取价格	100 TQFP
GS8640Z18T	GSI	获取价格	72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167	GSI	获取价格	72Mb Pipelined and Flow Through Synchronous NBT SRAM

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