5秒后页面跳转
GS8640Z18RT-250M PDF预览

GS8640Z18RT-250M

更新时间: 2024-09-26 14:52:51
品牌 Logo 应用领域
GSI /
页数 文件大小 规格书
25页 488K
描述
100 TQFP

GS8640Z18RT-250M 技术参数

生命周期:Active包装说明:LQFP, QFP100,.63X.87
Reach Compliance Code:compliant风险等级:5.73
最长访问时间:5.5 ns其他特性:IT ALSO OPERATES AT 3.3 V NOMINAL SUPPLY VOLTAGE
最大时钟频率 (fCLK):250 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100长度:20 mm
内存密度:75497472 bit内存集成电路类型:ZBT SRAM
内存宽度:18功能数量:1
端子数量:100字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:4MX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
座面最大高度:1.6 mm最大待机电流:0.12 A
最大压摆率:0.45 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
总剂量:50k Rad(Si) V宽度:14 mm
Base Number Matches:1

GS8640Z18RT-250M 数据手册

 浏览型号GS8640Z18RT-250M的Datasheet PDF文件第2页浏览型号GS8640Z18RT-250M的Datasheet PDF文件第3页浏览型号GS8640Z18RT-250M的Datasheet PDF文件第4页浏览型号GS8640Z18RT-250M的Datasheet PDF文件第5页浏览型号GS8640Z18RT-250M的Datasheet PDF文件第6页浏览型号GS8640Z18RT-250M的Datasheet PDF文件第7页 
GS81280Z18/36RT-333M/250M  
GS8640Z18/36RT-333M/250M  
GS8320Z18/36RT-333M/250M  
333 MHz250 MHz  
Rad-Tolerant SRAM  
144Mb/72Mb/36Mb PL/FT No Bus Turnaround SRAMs  
100-Pin TQFP  
Military Temp  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
SRAMs, allow utilization of all available bus bandwidth by  
eliminating the need to insert deselect cycles when the device  
is switched from read to write cycles.  
Features  
• Aerospace-Level Product  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb  
devices  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
The GS81280Z18/36RT, GS8640Z18/36RT, and  
GS8320Z18/36RT may be configured by the user to operate in  
Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, meaning that in addition to the rising edge  
triggered registers that capture input signals, the device  
incorporates a rising-edge-triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
• 100-pin TQFP package  
Radiation Performance  
• Total Ionizing Dose (TID) > 50krads(Si)  
• Destructive Single Event Latchup Immunity >37 MeV.cm2/mg  
(100C)  
Functional Description  
The GS81280Z18/36RT, GS8640Z18/36RT, and  
GS8320Z18/36RT are Synchronous Static SRAMs. GSI's NBT  
SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/  
double late write or flow through read/single late write  
The GS81280Z18/36RT, GS8640Z18/36RT, and  
GS8320Z18/36RT are implemented with GSI's high  
performance CMOS technology and are available in a JEDEC-  
standard 100-pin TQFP package.  
Parameter Synopsis  
-333M -250M  
Unit  
tKQ  
2.5  
3.0  
2.5  
4.0  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
530  
600  
430  
470  
mA  
mA  
tKQ  
tCycle  
4.5  
4.5  
5.5  
5.5  
ns  
ns  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
400  
435  
360  
380  
mA  
mA  
Rev: 1.01a 10/2020  
1/25  
© 2018, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

与GS8640Z18RT-250M相关器件

型号 品牌 获取价格 描述 数据表
GS8640Z18RT-333M GSI

获取价格

100 TQFP
GS8640Z18T GSI

获取价格

72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167 GSI

获取价格

72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167I GSI

获取价格

72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167IT GSI

获取价格

ZBT SRAM, 4MX18, 8ns, CMOS, PQFP100, TQFP-100
GS8640Z18T-167IV GSI

获取价格

72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167IVT GSI

获取价格

ZBT SRAM, 4MX18, 8ns, CMOS, PQFP100, TQFP-100
GS8640Z18T-167T GSI

获取价格

ZBT SRAM, 4MX18, 8ns, CMOS, PQFP100, TQFP-100
GS8640Z18T-167V GSI

获取价格

72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-167VT GSI

获取价格

ZBT SRAM, 4MX18, 8ns, CMOS, PQFP100, TQFP-100