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GS8640Z18T-200IVT PDF预览

GS8640Z18T-200IVT

更新时间： 2024-11-13 13:08:03
品牌 Logo 应用领域
GSI 静态存储器
页数 文件大小 规格书
25页 1035K
描述
ZBT SRAM, 4MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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GS8640Z18T-200IVT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.32最长访问时间：7.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLYJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：75497472 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8640Z18T-200IVT 数据手册

 浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第2页浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第3页浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第4页浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第5页浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第6页浏览型号GS8640Z18T-200IVT的Datasheet PDF文件第7页 
Product Preview  
GS8640Z18/36T-300/250/200/167  
300 MHz–167 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
72Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
The GS8640Z18/36T may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, meaning that in addition to the rising edge  
triggered registers that capture input signals, the device  
incorporates a rising-edge-triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8640Z18/36T is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 100-pin TQFP package.  
Parameter Synopsis  
-300  
-250  
-200  
-167  
Unit  
t
2.3  
3.3  
2.5  
4.0  
3.0  
5.0  
3.5  
6.0  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
400  
480  
340  
410  
290  
350  
260  
305  
mA  
mA  
t
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
285  
330  
245  
280  
220  
250  
210  
240  
mA  
mA  
*All GSI Technology packages are at least 5/6 RoHS compliant.  
Packages listed with the additional “G” designator are 6/6 RoHS compliant.  
Rev: 1.01 1/2006  
1/25  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS8640Z18T-250I GSI

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GS8640Z18T-250IV GSI

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 		72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z18T-250T GSI

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GS8640Z18T-250V GSI

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