Datasheet > 暂无类别数据> GS832018GT-225I

GS832018GT-225I

更新时间： 2024-11-19 07:02:07

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
25页	645K
描述
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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GS832018GT-225I 数据手册

Preliminary

GS832018/32/36T-250/225/200/166/150/133

250 MHz–133 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Byte Write and Global Write

Functional Description

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS832018/32/36T is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Core and Interface Voltages

The GS832018/32/36T operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

2.5 2.7 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

Pipeline

3-1-1-1

tCycle

Curr (x18) 285 265 245 220 210 185 mA

Curr (x32/x36) 350 320 295 260 240 215 mA

6.5 7.0 7.5 8.0 8.5 8.5 ns

Flow

Through

2-1-1-1

tCycle

Curr (x18) 205 195 185 175 165 155 mA

Curr (x32/x36) 235 225 210 200 190 175 mA

Rev: 1.02 10/2004

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...25

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与GS832018GT-225I相关器件

型号	品牌	获取价格	描述	数据表
GS832018GT-225IV	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-225T	GSI	获取价格	Cache SRAM, 2MX18, 7ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832018GT-225V	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-250	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-250I	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-250IT	GSI	获取价格	Cache SRAM, 2MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832018GT-250IV	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-250IVT	GSI	获取价格	Cache SRAM, 2MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS832018GT-250V	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832018GT-250VT	GSI	获取价格	暂无描述

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