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GS8162Z18B-200IT PDF预览

GS8162Z18B-200IT

更新时间： 2024-11-05 15:42:51
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
35页 1495K
描述
ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, FBGA-119

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GS8162Z18B-200IT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.68最长访问时间：6.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5,2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.99 mm最大待机电流：0.03 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.225 mA最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS8162Z18B-200IT 数据手册

 浏览型号GS8162Z18B-200IT的Datasheet PDF文件第2页浏览型号GS8162Z18B-200IT的Datasheet PDF文件第3页浏览型号GS8162Z18B-200IT的Datasheet PDF文件第4页浏览型号GS8162Z18B-200IT的Datasheet PDF文件第5页浏览型号GS8162Z18B-200IT的Datasheet PDF文件第6页浏览型号GS8162Z18B-200IT的Datasheet PDF文件第7页 
GS8162Z18(B/D)/GS8162Z36(B/D)  
250 MHz–133 MHz 2.5  
119, 165-bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2M, 4M, and 8M devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119- and 165-Bump BGA packages  
The GS8162Z18(B/D)/36(B/D) may be configured by the user  
to operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8162Z18(B/D)/36(B/D) is an 18Mbit Synchronous  
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL  
or other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS8162Z18(B/D)/36(B/D) is implemented with GSI's  
high performance CMOS technology and is available in a  
JEDEC-standard 119-bump and 165-bump BGA packages.  
Parameter Synopsis  
-250  
-225  
-200  
-166  
-150 -133 Unit  
Pipeline  
3-1-1-1  
tKQ  
2.5  
4.0  
2.7  
4.4  
3.0  
5.0  
3.4  
6.0  
3.8  
6.7  
4.0  
7.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
280  
330  
255  
300  
230  
270  
200  
230  
185  
215  
165  
190  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
275  
320  
250  
295  
230  
265  
195  
225  
180  
210  
165  
185  
mA  
mA  
Flow Through  
2-1-1-1  
tKQ  
5.5  
5.5  
6.0  
6.0  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
tCycle  
Curr (x18)  
Curr (x36)  
175  
200  
165  
190  
160  
180  
150  
170  
145  
165  
135  
150  
mA  
mA  
3.3 V  
2.5 V  
Curr (x18)  
Curr (x36)  
175  
200  
165  
190  
160  
180  
150  
170  
145  
165  
135  
150  
mA  
mA  
Rev: 2.22 11/2005  
1/35  
© 1999, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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 		ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, FBGA-119
GS8162Z18B-225 GSI

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 		18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18B-225I GSI

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GS8162Z18B-225IT GSI

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 		ZBT SRAM, 1MX18, 6ns, CMOS, PBGA119, FBGA-119
GS8162Z18B-225T GSI

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 		ZBT SRAM, 1MX18, 6ns, CMOS, PBGA119, FBGA-119
GS8162Z18B-250 GSI

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 		18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18B-250I GSI

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 		18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18B-250IT GSI

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 		ZBT SRAM, 1MX18, 5.5ns, CMOS, PBGA119, FBGA-119
GS8162Z18B-250T GSI

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 		ZBT SRAM, 1MX18, 5.5ns, CMOS, PBGA119, FBGA-119
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 		18Mb Pipelined and Flow Through Synchronous NBT SRAM

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