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GS8162Z18BB-200IVT PDF预览

GS8162Z18BB-200IVT

更新时间: 2024-11-05 13:07:59
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
34页 1555K
描述
ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, FPBGA-119

GS8162Z18BB-200IVT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:FPBGA-119针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.68
最长访问时间:6.5 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLY
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:ZBT SRAM内存宽度:18
功能数量:1端子数量:119
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX18
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.99 mm
最大供电电压 (Vsup):2 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

GS8162Z18BB-200IVT 数据手册

 浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第2页浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第3页浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第4页浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第5页浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第6页浏览型号GS8162Z18BB-200IVT的Datasheet PDF文件第7页 
GS8162Z18/36B(B/D)  
250 MHz150 MHz  
119- & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• On-chip write parity checking; even or odd selectable  
• On-chip parity encoding and error detection  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2M, 4M, and 8M devices  
• Byte write operation (9-bit Bytes)  
The GS8162Z18/36B(B/D) may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119-bump and 165-bump BGA packages  
• RoHS-compliant 119-bump and 165-bump BGA packages  
available  
Functional Description  
The GS8162Z18/36B(B/D) is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump or 165-bump BGA package.  
The GS8162Z18/36B(B/D) is an 18Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
ns  
ns  
tKQ  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
tCycle  
Pipeline  
3-1-1-1  
mA  
mA  
295  
345  
245  
285  
200  
225  
Curr (x18)  
Curr (x36)  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
mA  
mA  
225  
255  
200  
220  
185  
205  
Curr (x18)  
Curr (x36)  
Rev: 1.04a 2/2006  
1/34  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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