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GS8162Z18BB-250IV PDF预览

GS8162Z18BB-250IV

更新时间: 2024-11-05 03:54:03
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
33页 1561K
描述
18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162Z18BB-250IV 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:FPBGA-119针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.68
Is Samacsys:N最长访问时间:5.5 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLYJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:18874368 bit内存集成电路类型:ZBT SRAM
内存宽度:18功能数量:1
端子数量:119字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX18封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.99 mm最大供电电压 (Vsup):2 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

GS8162Z18BB-250IV 数据手册

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Preliminary  
GS8162ZxxB(B/D)-xxxV  
250 MHz150 MHz  
119- & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
18Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 1.8 V or 2.5 V core power supply  
• 1.8 V or 2.5 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• On-chip write parity checking; even or odd selectable  
• On-chip parity encoding and error detection  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 2M, 4M, and 8M devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119- and 165-bump BGA packages  
• RoHS-compliant 119- and 165-bump BGA packages  
available  
The GS8162ZxxB(B/D)-xxxV may be configured by the user  
to operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, in addition to the rising-edge-  
triggered registers that capture input signals, the device  
incorporates a rising edge triggered output register. For read  
cycles, pipelined SRAM output data is temporarily stored by  
the edge-triggered output register during the access cycle and  
then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS8162ZxxB(B/D)-xxxV is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump or 165-bump BGA package.  
The GS8162ZxxB(B/D)-xxxV is an 18Mbit Synchronous  
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL  
or other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
3.0  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
280  
330  
230  
270  
185  
210  
mA  
mA  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
Flow Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
210  
240  
185  
205  
170  
190  
mA  
mA  
Rev: 1.01a 6/2006  
1/33  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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