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GS816273CGC-250 PDF预览

GS816273CGC-250

更新时间： 2024-11-18 05:10:43
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
28页 1258K
描述
256K x 72 18Mb S/DCD Sync Burst SRAMs

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GS816273CGC-250 数据手册

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Preliminary  
GS816273CC-333/300/250  
333 MHz–250 MHz  
209-Bump BGA  
Commercial Temp  
Industrial Temp  
256K x 72  
18Mb S/DCD Sync Burst SRAMs  
3.3 V or 2.5 V V  
DD  
3.3 V or 2.5 V I/O  
with the Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 3.3 V or 2.5 V core power supply  
SCD and DCD Pipelined Reads  
The GS816273CC is an SCD (Single Cycle Deselect) and DCD (Dual  
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs  
pipeline disable commands to the same degree as read commands.  
SCD SRAMs pipeline deselect commands one stage less than read  
commands. SCD RAMs begin turning off their outputs immediately  
after the deselect command has been captured in the input registers.  
DCD RAMs hold the deselect command for one full cycle and then  
begin turning off their outputs just after the second rising edge of  
clock. The user may configure this SRAM for either mode of  
operation using the SCD mode input.  
• 3.3 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 209-bump BGA package  
• RoHS-compliant 209-bump BGA package available  
Byte Write and Global Write  
Functional Description  
Byte write operation is performed by using Byte Write enable (BW)  
input combined with one or more individual byte write signals (Bx).  
In addition, Global Write (GW) is available for writing all bytes at one  
time, regardless of the Byte Write control inputs.  
Applications  
The GS816273CC is an 18,874,368-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although of a  
type originally developed for Level 2 Cache applications supporting  
high performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main store to  
networking chip set support.  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ low) for  
multi-drop bus applications and normal drive strength (ZQ floating or  
high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control inputs  
Sleep Mode  
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are  
synchronous and are controlled by a positive-edge-triggered clock  
input (CK). Output enable (G) and power down control (ZZ) are  
asynchronous inputs. Burst cycles can be initiated with either ADSP  
or ADSC inputs. In Burst mode, subsequent burst addresses are  
generated internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or interleave order  
Low power (Sleep mode) is attained through the assertion (High) of  
the ZZ signal, or by stopping the clock (CK). Memory data is retained  
during Sleep mode.  
Core and Interface Voltages  
The GS816273CC operates on a 3.3 V or 2.5 V power supply. All  
inputs are 3.3 V or 2.5 V compatible. Separate output power (VDDQ  
)
pins are used to decouple output noise from the internal circuits and  
are 3.3 V or 2.5 V compatible.  
Parameter Synopsis  
-333  
-300  
-250  
Unit  
tKQ  
tCycle  
Curr  
2.8  
3.0  
2.8  
3.3  
3.0  
4.0  
ns  
ns  
Pipeline  
3-1-1-1  
545  
495  
425  
mA  
Rev: 1.01a 6/2006  
1/28  
© 2005, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS816273CGC-250I GSI

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 		256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816273CGC-250IV GSI

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GS816273CGC-250V GSI

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GS816273CGC-300 GSI

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GS816273CGC-300I GSI

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GS816273CGC-333 GSI

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GS816273CGC-333I GSI

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 		256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816273GC-133T GSI

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 		Cache SRAM, 256KX72, 3.5ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
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 		Cache SRAM, 256KX72, 3.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
GS816273GC-150IT GSI

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 		Cache SRAM, 256KX72, 3.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

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