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Datasheet > GS816273CGC-250V
GS816273CGC-250V PDF预览

GS816273CGC-250V

更新时间： 2024-11-18 05:10:43
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
28页 1205K
描述
256K x 72 18Mb S/DCD Sync Burst SRAMs

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中文翻译

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GS816273CGC-250V 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LBGA,针数：209
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41Factory Lead Time：8 weeks
风险等级：5.62最长访问时间：2.5 ns
其他特性：PIPELINED ARCHITECTURE AND ALSO OPERATES AT 2.5 VJESD-30 代码：R-PBGA-B209
JESD-609代码：e1长度：22 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：72湿度敏感等级：3
功能数量：1端子数量：209
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX72
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.7 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

GS816273CGC-250V 数据手册

 浏览型号GS816273CGC-250V的Datasheet PDF文件第2页浏览型号GS816273CGC-250V的Datasheet PDF文件第3页浏览型号GS816273CGC-250V的Datasheet PDF文件第4页浏览型号GS816273CGC-250V的Datasheet PDF文件第5页浏览型号GS816273CGC-250V的Datasheet PDF文件第6页浏览型号GS816273CGC-250V的Datasheet PDF文件第7页 
Preliminary  
GS816273CC-250V  
250 MHz  
209-Bump BGA  
Commercial Temp  
Industrial Temp  
256K x 72  
18Mb S/DCD Sync Burst SRAMs  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
with the Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 1.8 V or 2.5 V core power supply  
SCD and DCD Pipelined Reads  
The GS816273CC-250V is an SCD (Single Cycle Deselect) and DCD  
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs  
pipeline disable commands to the same degree as read commands.  
SCD SRAMs pipeline deselect commands one stage less than read  
commands. SCD RAMs begin turning off their outputs immediately  
after the deselect command has been captured in the input registers.  
DCD RAMs hold the deselect command for one full cycle and then  
begin turning off their outputs just after the second rising edge of  
clock. The user may configure this SRAM for either mode of  
operation using the SCD mode input.  
• 1.8 V or 2.5 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 209-bump BGA package  
• RoHS-compliant 209-bump BGA package available  
Byte Write and Global Write  
Functional Description  
Byte write operation is performed by using Byte Write enable (BW)  
input combined with one or more individual byte write signals (Bx).  
In addition, Global Write (GW) is available for writing all bytes at one  
time, regardless of the Byte Write control inputs.  
Applications  
The GS816273CC-250V is an 18,874,368-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although of a  
type originally developed for Level 2 Cache applications supporting  
high performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main store to  
networking chip set support.  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ low) for  
multi-drop bus applications and normal drive strength (ZQ floating or  
high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control inputs  
Sleep Mode  
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are  
synchronous and are controlled by a positive-edge-triggered clock  
input (CK). Output enable (G) and power down control (ZZ) are  
asynchronous inputs. Burst cycles can be initiated with either ADSP  
or ADSC inputs. In Burst mode, subsequent burst addresses are  
generated internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or interleave order  
Low power (Sleep mode) is attained through the assertion (High) of  
the ZZ signal, or by stopping the clock (CK). Memory data is retained  
during Sleep mode.  
Core and Interface Voltages  
The GS816273CC-250V operates on a 1.8 V or 2.5 V power supply.  
All inputs are 1.8 V or 2.5 V compatible. Separate output power  
(VDDQ) pins are used to decouple output noise from the internal  
circuits and are 1.8 V or 2.5 V compatible.  
Parameter Synopsis  
-250  
Unit  
tKQ  
tCycle  
Curr  
3.0  
4.0  
ns  
ns  
Pipeline  
3-1-1-1  
425  
mA  
Rev: 1.01a 6/2006  
1/28  
© 2005, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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中文翻译

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