Datasheet > GS81302D07E-375

GS81302D07E-375

更新时间： 2024-12-01 10:06:43

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
33页	463K
描述
DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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数据手册

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GS81302D07E-375 数据手册

Preliminary

GS81302D07/10/19/37E-400/375/333/300

400 MHz–300 MHz

144Mb SigmaQuad-II+^TM

Burst of 4 SRAM

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V and 1.5 V I/O

Features

• 2.0 clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

Clocking and Addressing Schemes

The GS81302D07/10/19/37E are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 8M x 18 has a 2M addressable index).

Parameter Synopsis

-400

2.5 ns

0.45 ns

-375

-333

-300

3.3 ns

0.45 ns

tKHKH

tKHQV

2.66 ns

0.45 ns

3.0 ns

0.45 ns

Rev: 1.02b 6/2010

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...33

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与GS81302D07E-375相关器件

型号	品牌	获取价格	描述	数据表
GS81302D07E-375IT	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GS81302D07E-400	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07E-400I	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07E-450	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07E-450I	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07GE-300	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07GE-300I	GSI	获取价格	144Mb SigmaQuad-IITM Burst of 4 SRAM
GS81302D07GE-333	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302D07GE-333I	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS81302D07GE-333T	GSI	获取价格	DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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