Datasheet > GS81302D08E-200IT

GS81302D08E-200IT

更新时间： 2024-12-02 09:35:19

品牌	Logo	应用领域
GSI		双倍数据速率静态存储器
页数	文件大小	规格书
39页	628K
描述
DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

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Preliminary

GS81302D08/09/18/36E-333/300/250/200/167

333 MHz–167 MHz

1.8 V V

1.8 V and 1.5 V I/O

165-Bump BGA

Commercial Temp

Industrial Temp

144Mb SigmaQuad -II

Burst of 4 SRAM

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

SigmaQuad™ Family Overview

1 mm Bump Pitch, 11 x 15 Bump Array

The GS81302D08/09/18/36E are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D08/09/18/36E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B4 RAMs always transfer

data in four packets, A0 and A1 are internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfers. Because the LSBs are tied off internally,

the address field of a SigmaQuad-II B4 RAM is always two

address pins less than the advertised index depth (e.g., the 8M

x 18 has a 2M addressable index).

Clocking and Addressing Schemes

The GS81302D08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Parameter Synopsis

- 333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.50 ns

tKHKH

tKHQV

Rev: 1.02a 6/2010

1/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...39

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与GS81302D08E-200IT相关器件

型号	品牌	获取价格	描述	数据表
GS81302D08E-250	GSI	获取价格	165 BGA
GS81302D08E-250I	GSI	获取价格	165 BGA
GS81302D08E-300	GSI	获取价格	165 BGA
GS81302D08E-300I	GSI	获取价格	165 BGA
GS81302D08E-333	GSI	获取价格	165 BGA
GS81302D08E-333I	GSI	获取价格	165 BGA
GS81302D08E-350	GSI	获取价格	165 BGA
GS81302D08E-350I	GSI	获取价格	165 BGA
GS81302D08E-375	GSI	获取价格	165 BGA
GS81302D08E-375I	GSI	获取价格	165 BGA

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