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GS81302D07GE-375IT PDF预览

GS81302D07GE-375IT

更新时间: 2024-11-30 14:42:23
品牌 Logo 应用领域
GSI 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
33页 463K
描述
DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS81302D07GE-375IT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.56
Is Samacsys:N最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:17 mm
内存密度:134217728 bit内存集成电路类型:DDR SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:165
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16MX8
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm
Base Number Matches:1

GS81302D07GE-375IT 数据手册

 浏览型号GS81302D07GE-375IT的Datasheet PDF文件第2页浏览型号GS81302D07GE-375IT的Datasheet PDF文件第3页浏览型号GS81302D07GE-375IT的Datasheet PDF文件第4页浏览型号GS81302D07GE-375IT的Datasheet PDF文件第5页浏览型号GS81302D07GE-375IT的Datasheet PDF文件第6页浏览型号GS81302D07GE-375IT的Datasheet PDF文件第7页 
Preliminary  
GS81302D07/10/19/37E-400/375/333/300  
400 MHz–300 MHz  
144Mb SigmaQuad-II+TM  
Burst of 4 SRAM  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• 2.0 clock Latency  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 4 Read and Write  
• On-Die Termination (ODT) on Data (D), Byte Write (BW),  
and Clock (K, K) inputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• Data Valid Pin (QVLD) Support  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
SigmaQuadFamily Overview  
Clocking and Addressing Schemes  
The GS81302D07/10/19/37E are built in compliance with the  
SigmaQuad-II+ SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 150,994,944-bit (144Mb)  
SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs  
are just one element in a family of low power, low voltage  
HSTL I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking systems.  
The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
Because Separate I/O SigmaQuad-II+ B4 RAMs always  
transfer data in four packets, A0 and A1 are internally set to 0  
for the first read or write transfer, and automatically  
incremented by 1 for the next transfers. Because the LSBs are  
tied off internally, the address field of a SigmaQuad-II+ B4  
RAM is always two address pins less than the advertised index  
depth (e.g., the 8M x 18 has a 2M addressable index).  
Parameter Synopsis  
-400  
2.5 ns  
0.45 ns  
-375  
-333  
-300  
3.3 ns  
0.45 ns  
tKHKH  
tKHQV  
2.66 ns  
0.45 ns  
3.0 ns  
0.45 ns  
Rev: 1.02b 6/2010  
1/33  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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