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GM71VS64803CLJ-6 PDF预览

GM71VS64803CLJ-6

更新时间： 2024-01-09 06:06:40
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
11页 112K
描述
x8 EDO Page Mode DRAM

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中文翻译

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GM71VS64803CLJ-6 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.83
访问模式：FAST PAGE WITH EDO最长访问时间：60 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH; BATTERY BACKUP OPERATIONI/O 类型：COMMON
JESD-30 代码：R-PDSO-J32JESD-609代码：e0
内存密度：67108864 bit内存集成电路类型：EDO DRAM
内存宽度：8功能数量：1
端口数量：1端子数量：32
字数：8388608 words字数代码：8000000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装等效代码：SOJ32,.44
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified刷新周期：8192
自我刷新：YES最大待机电流：0.0003 A
子类别：DRAMs最大压摆率：0.135 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

GM71VS64803CLJ-6 数据手册

 浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第5页浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第6页浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第7页浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第9页浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第10页浏览型号GM71VS64803CLJ-6的Datasheet PDF文件第11页 
GM71V64803C  
GM71VS64803CL  
Notes:  
T
AC measurements assume t = 2  
ns  
.
1.  
2.  
AC initial pause of 200  
is required after power up followed by a minimum of eight  
us  
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-  
RAS refresh)  
RCD  
RAC  
RCD  
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a  
3.  
4.  
5.  
RCD  
RCD  
reference point only: if t  
controlled exclusively by t  
is greater than the specified t  
(max) limit, then access time is  
CAC  
.
RAD  
RAC  
RAD  
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a  
RAD  
RAD  
reference point only: if t  
controlled exclusively by t .  
is greater than the specified t  
(max) limit, then access time is  
AA  
OED  
CDD  
Either t or t must be satisfied.  
DZO  
DZC  
6. Either t or t must be satisfied.  
IH  
IL  
7. V (min) and V (max) are reference levels for measuring timing of input signals. Also,  
IH  
IL  
transition times are measured between V (min) and V (max).  
£
£
RAD  
RCD  
RCD  
t
RAD  
RCD  
RAD  
8. Assumes that t  
(max) and t  
t
(max). If t  
or t is greater than the maximum  
RAC  
recommended value shown in this table, t exceeds the value shown.  
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.  
³
³
RCD  
RAD  
RCD  
RCD  
CAC  
RAD  
AA  
10. Assumes that t  
t
(max) and t + t (max)  
t
+ t (max).  
³
£
RAD  
11.  
RAD  
t
RCD  
CAC  
AA  
Assumes that t  
(max) and t +t (max)  
t
+t (max).  
12.  
RCH  
RRH  
Either t or t must be satisfied for a read cycles.  
OFF  
t
OEZ(  
OFR  
WEZ  
13.  
(max), t max), t (max) and t (max) define the time at which the outputs achieve the  
open circuit condition and is not referenced to output voltage levels.  
WCS  
RWD  
CWD, AWD,  
CPW  
14.  
t
, t  
data sheet as electrical characteristics only: if t  
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if  
, t  
t
and t  
are not restrictive operating parameters. They are included in the  
³
WCS  
WCS  
t
(min), the cycle is an early write cycle  
³
³
³
³
RWD  
t
RWD  
CWD  
CWD  
AWD  
AWD  
CPW  
CPW  
t
t
(min), t  
t
(min), t  
t
(min) and t  
(min), the cycle is a read-  
modify-write and the data output will contain data read from the selected cell: if neither of the  
above sets of conditions is satisfied, the condition of the data out (at access time) is  
indeterminate.  
DS  
DH  
15.  
t and t are referred to CAS leading edge in early write cycles and to WE leading edge in  
delayed write or read-modify-write cycles.  
RASP  
16.  
17.  
18.  
t
defines RAS pulse width in extended data out mode cycles.  
AA, CAC  
CPA  
and t  
Access time is determined by the longest among t  
t
.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying  
data to the device.  
19.  
When output buffers are enabled once, sustain the low impedance state until valid daa is  
obtained. When output buffer is turned on and off within a very short time, generally it causes  
CC  
SS  
IH  
IL  
large V /V line noise, which causes to degrade V min/V max level.  
Rev 0.1 / Apr’01  
1...567891011

中文翻译

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